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[PULL 12/53] ppc: Add support for 'mffsce' instruction
From: |
David Gibson |
Subject: |
[PULL 12/53] ppc: Add support for 'mffsce' instruction |
Date: |
Fri, 4 Oct 2019 19:37:06 +1000 |
From: "Paul A. Clarke" <address@hidden>
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.
'mffsce' is identical to 'mffs', except that it also clears the exception
enable bits in the FPSCR.
On CPUs without support for 'mffsce' (below ISA 3.0), the
instruction will execute identically to 'mffs'.
Signed-off-by: Paul A. Clarke <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++
target/ppc/translate/fp-ops.inc.c | 2 ++
2 files changed, 32 insertions(+)
diff --git a/target/ppc/translate/fp-impl.inc.c
b/target/ppc/translate/fp-impl.inc.c
index 75f9523b07..d8e27bf4d5 100644
--- a/target/ppc/translate/fp-impl.inc.c
+++ b/target/ppc/translate/fp-impl.inc.c
@@ -639,6 +639,36 @@ static void gen_mffsl(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
+/* mffsce */
+static void gen_mffsce(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i32 mask;
+
+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
+ return gen_mffs(ctx);
+ }
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+
+ t0 = tcg_temp_new_i64();
+
+ gen_reset_fpstatus();
+ tcg_gen_extu_tl_i64(t0, cpu_fpscr);
+ set_fpr(rD(ctx->opcode), t0);
+
+ /* Clear exception enable bits in the FPSCR. */
+ tcg_gen_andi_i64(t0, t0, ~FP_ENABLES);
+ mask = tcg_const_i32(0x0003);
+ gen_helper_store_fpscr(cpu_env, t0, mask);
+
+ tcg_temp_free_i32(mask);
+ tcg_temp_free_i64(t0);
+}
+
static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
{
TCGv_i64 t0 = tcg_temp_new_i64();
diff --git a/target/ppc/translate/fp-ops.inc.c
b/target/ppc/translate/fp-ops.inc.c
index f2bcf0e67b..88fab65628 100644
--- a/target/ppc/translate/fp-ops.inc.c
+++ b/target/ppc/translate/fp-ops.inc.c
@@ -105,6 +105,8 @@ GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001,
PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
+GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
+ PPC2_ISA300),
GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
--
2.21.0
- [PULL 00/53] ppc-for-4.2 queue 20191004, David Gibson, 2019/10/04
- [PULL 05/53] spapr: Report kvm_irqchip_in_kernel() in 'info pic', David Gibson, 2019/10/04
- [PULL 02/53] ppc/pnv: fix "bmc" node name in DT, David Gibson, 2019/10/04
- [PULL 03/53] spapr-tpm-proxy: Drop misleading check, David Gibson, 2019/10/04
- [PULL 01/53] pseries: do not allow memory-less/cpu-less NUMA node, David Gibson, 2019/10/04
- [PULL 06/53] hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARs, David Gibson, 2019/10/04
- [PULL 09/53] spapr/irq: Introduce an ics_irq_free() helper, David Gibson, 2019/10/04
- [PULL 12/53] ppc: Add support for 'mffsce' instruction,
David Gibson <=
- [PULL 10/53] spapr/irq: Only claim VALID interrupts at the KVM level, David Gibson, 2019/10/04
- [PULL 07/53] hw/ppc/pnv_occ: add sram device model for occ common area, David Gibson, 2019/10/04
- [PULL 04/53] hw/ppc/pnv: fix checkpatch.pl coding style warnings, David Gibson, 2019/10/04
- [PULL 11/53] ppc: Add support for 'mffscrn','mffscrni' instructions, David Gibson, 2019/10/04
- [PULL 14/53] ppc/kvm: Skip writing DPDES back when in run time state, David Gibson, 2019/10/04
- [PULL 13/53] ppc: Use FPSCR defines instead of constants, David Gibson, 2019/10/04
- [PULL 08/53] hw/ppc/pnv_homer: add PowerNV homer device model, David Gibson, 2019/10/04
- [PULL 24/53] target/ppc: update {get, set}_dfp{64, 128}() helper functions to read/write DFP numbers correctly, David Gibson, 2019/10/04
- [PULL 16/53] spapr: Move handling of special NVLink numa node from reset to init, David Gibson, 2019/10/04
- [PULL 20/53] spapr: Stop providing RTAS blob, David Gibson, 2019/10/04