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[PATCH v5 18/22] target/arm: Enable MTE
From: |
Richard Henderson |
Subject: |
[PATCH v5 18/22] target/arm: Enable MTE |
Date: |
Fri, 11 Oct 2019 09:47:40 -0400 |
We now implement all of the components of MTE, without actually
supporting any tagged memory. All MTE instructions will work,
trivially, so we can enable support.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 10 ++++++++++
target/arm/cpu64.c | 1 +
2 files changed, 11 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2399c14471..12fffa3ee4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -209,6 +209,16 @@ static void arm_cpu_reset(CPUState *s)
* make no difference to the user-level emulation.
*/
env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
+ /* Enable MTE allocation tags. */
+ env->cp15.hcr_el2 |= HCR_ATA;
+ env->cp15.scr_el3 |= SCR_ATA;
+ env->cp15.sctlr_el[1] |= SCTLR_ATA0;
+ /* Enable synchronous tag check failures. */
+ env->cp15.sctlr_el[1] |= 1ull << 38;
+#ifdef TARGET_AARCH64
+ /* Set MTE seed to non-zero value, otherwise RandomTag fails. */
+ env->cp15.rgsr_el1 = 0x123400;
+#endif
#else
/* Reset into the highest available EL */
if (arm_feature(env, ARM_FEATURE_EL3)) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index d7f5bf610a..ac1e2dc2c4 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -350,6 +350,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64pfr1;
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
cpu->isar.id_aa64pfr1 = t;
t = cpu->isar.id_aa64mmfr1;
--
2.17.1
- [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions, (continued)
- [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions, Richard Henderson, 2019/10/11
- [PATCH v5 08/22] target/arm: Implement the GMI instruction, Richard Henderson, 2019/10/11
- [PATCH v5 09/22] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/10/11
- [PATCH v5 12/22] target/arm: Implement the STGP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/10/11
- [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/10/11
- [PATCH v5 14/22] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/10/11
- [PATCH v5 15/22] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/10/11
- [PATCH v5 16/22] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/10/11
- [PATCH v5 18/22] target/arm: Enable MTE,
Richard Henderson <=
- [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/10/11
- [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2019/10/11
- [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory, Richard Henderson, 2019/10/11
- [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/10/11
- [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/10/11
- Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, no-reply, 2019/10/11
- Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, Evgenii Stepanov, 2019/10/15