[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 15/55] atomic_template: add inline trace/plugin helpers
|
From: |
Alex Bennée |
|
Subject: |
[PATCH v5 15/55] atomic_template: add inline trace/plugin helpers |
|
Date: |
Mon, 14 Oct 2019 11:49:08 +0100 |
From: "Emilio G. Cota" <address@hidden>
In preparation for plugin support.
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
v4
- move common stuff to atomic_common.inc.c
- fix ups for widened uint16_t info
- drop haddr in helpers
- fix wide lines
---
accel/tcg/atomic_common.inc.c | 50 +++++++++++++++++++
accel/tcg/atomic_template.h | 93 +++++++++++++++++++++--------------
accel/tcg/cputlb.c | 2 +
accel/tcg/user-exec.c | 2 +
4 files changed, 111 insertions(+), 36 deletions(-)
create mode 100644 accel/tcg/atomic_common.inc.c
diff --git a/accel/tcg/atomic_common.inc.c b/accel/tcg/atomic_common.inc.c
new file mode 100644
index 0000000000..a86098fb2d
--- /dev/null
+++ b/accel/tcg/atomic_common.inc.c
@@ -0,0 +1,50 @@
+/*
+ * Common Atomic Helper Functions
+ *
+ * This file should be included before the various instantiations of
+ * the atomic_template.h helpers.
+ *
+ * Copyright (c) 2019 Linaro
+ * Written by Alex Bennée <address@hidden>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+static inline
+void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ CPUState *cpu = env_cpu(env);
+
+ trace_guest_mem_before_exec(cpu, addr, info);
+ trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
+}
+
+static inline void
+atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
+
+static inline
+void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
+
+static inline
+void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index dfeddf6a54..84d3370bf0 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -59,26 +59,6 @@
# define ABI_TYPE uint32_t
#endif
-#define ATOMIC_TRACE_RMW do { \
- uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
ATOMIC_MMU_IDX); \
- \
- trace_guest_mem_before_exec(env_cpu(env), addr, info); \
- trace_guest_mem_before_exec(env_cpu(env), addr, \
- info | TRACE_MEM_ST); \
- } while (0)
-
-#define ATOMIC_TRACE_LD do { \
- uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
ATOMIC_MMU_IDX); \
- \
- trace_guest_mem_before_exec(env_cpu(env), addr, info); \
- } while (0)
-
-# define ATOMIC_TRACE_ST do { \
- uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true,
ATOMIC_MMU_IDX); \
- \
- trace_guest_mem_before_exec(env_cpu(env), addr, info); \
- } while (0)
-
/* Define host-endian atomic operations. Note that END is used within
the ATOMIC_NAME macro, and redefined below. */
#if DATA_SIZE == 1
@@ -98,14 +78,17 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env,
target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
DATA_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, cmpv, newv);
#else
ret = atomic_cmpxchg__nocheck(haddr, cmpv, newv);
#endif
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return ret;
}
@@ -115,10 +98,13 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong
addr EXTRA_ARGS)
{
ATOMIC_MMU_DECLS;
DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_LD;
+ atomic_trace_ld_pre(env, addr, info);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_ld_post(env, addr, info);
return val;
}
@@ -127,10 +113,13 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
{
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_ST;
+ atomic_trace_st_pre(env, addr, info);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_st_post(env, addr, info);
}
#endif
#else
@@ -140,10 +129,13 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env,
target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
DATA_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
ret = atomic_xchg__nocheck(haddr, val);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return ret;
}
@@ -154,10 +146,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong
addr, \
ATOMIC_MMU_DECLS; \
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
DATA_TYPE ret; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
ret = atomic_##X(haddr, val); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return ret; \
}
@@ -186,8 +182,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong
addr, \
ATOMIC_MMU_DECLS; \
XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
XDATA_TYPE cmp, old, new, val = xval; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
smp_mb(); \
cmp = atomic_read__nocheck(haddr); \
do { \
@@ -195,6 +194,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong
addr, \
cmp = atomic_cmpxchg__nocheck(haddr, old, new); \
} while (cmp != old); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return RET; \
}
@@ -232,14 +232,18 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env,
target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
DATA_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
#else
ret = atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
#endif
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return BSWAP(ret);
}
@@ -249,10 +253,14 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong
addr EXTRA_ARGS)
{
ATOMIC_MMU_DECLS;
DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_LD;
+ atomic_trace_ld_pre(env, addr, info);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_ld_post(env, addr, info);
return BSWAP(val);
}
@@ -261,11 +269,16 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
{
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ true,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_ST;
+ val = BSWAP(val);
+ atomic_trace_st_pre(env, addr, info);
val = BSWAP(val);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_st_post(env, addr, info);
}
#endif
#else
@@ -275,10 +288,14 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env,
target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
ABI_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
ret = atomic_xchg__nocheck(haddr, BSWAP(val));
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return BSWAP(ret);
}
@@ -289,10 +306,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong
addr, \
ATOMIC_MMU_DECLS; \
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
DATA_TYPE ret; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
ret = atomic_##X(haddr, BSWAP(val)); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return BSWAP(ret); \
}
@@ -319,8 +340,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong
addr, \
ATOMIC_MMU_DECLS; \
XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
XDATA_TYPE ldo, ldn, old, new, val = xval; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
smp_mb(); \
ldn = atomic_read__nocheck(haddr); \
do { \
@@ -328,6 +352,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong
addr, \
ldn = atomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \
} while (ldo != ldn); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return RET; \
}
@@ -355,10 +380,6 @@ GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new)
#undef MEND
#endif /* DATA_SIZE > 1 */
-#undef ATOMIC_TRACE_ST
-#undef ATOMIC_TRACE_LD
-#undef ATOMIC_TRACE_RMW
-
#undef BSWAP
#undef ABI_TYPE
#undef DATA_TYPE
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 9cf9e6455e..b587d910f8 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1825,6 +1825,8 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong
addr, uint64_t val,
#define ATOMIC_MMU_CLEANUP
#define ATOMIC_MMU_IDX oi
+#include "atomic_common.inc.c"
+
#define DATA_SIZE 1
#include "atomic_template.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index e9a58c5331..6b20510994 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -756,6 +756,8 @@ static void *atomic_mmu_lookup(CPUArchState *env,
target_ulong addr,
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
#define EXTRA_ARGS
+#include "atomic_common.inc.c"
+
#define DATA_SIZE 1
#include "atomic_template.h"
--
2.20.1
- [PATCH v5 03/55] cpu: introduce cpu_in_exclusive_context(), (continued)
- [PATCH v5 03/55] cpu: introduce cpu_in_exclusive_context(), Alex Bennée, 2019/10/14
- [PATCH v5 06/55] configure: add --enable-plugins (MOVE TO END), Alex Bennée, 2019/10/14
- [PATCH v5 02/55] trace: add mmu_index to mem_info, Alex Bennée, 2019/10/14
- [PATCH v5 09/55] plugin: add implementation of the api, Alex Bennée, 2019/10/14
- [PATCH v5 10/55] queue: add QTAILQ_REMOVE_SEVERAL, Alex Bennée, 2019/10/14
- [PATCH v5 07/55] plugin: add user-facing API, Alex Bennée, 2019/10/14
- [PATCH v5 11/55] cputlb: document get_page_addr_code, Alex Bennée, 2019/10/14
- [PATCH v5 24/55] target/arm: fetch code with translator_ld, Alex Bennée, 2019/10/14
- [PATCH v5 22/55] plugin-gen: add plugin_insn_append, Alex Bennée, 2019/10/14
- [PATCH v5 15/55] atomic_template: add inline trace/plugin helpers,
Alex Bennée <=
- [PATCH v5 20/55] *-user: plugin syscalls, Alex Bennée, 2019/10/14
- [PATCH v5 25/55] target/ppc: fetch code with translator_ld, Alex Bennée, 2019/10/14
- [PATCH v5 12/55] cputlb: introduce get_page_addr_code_hostp, Alex Bennée, 2019/10/14
- [PATCH v5 50/55] include/exec: wrap cpu_ldst.h in CONFIG_TCG, Alex Bennée, 2019/10/14
- [PATCH v5 21/55] cpu: hook plugin vcpu events, Alex Bennée, 2019/10/14
- [PATCH v5 37/55] vl: support -plugin option, Alex Bennée, 2019/10/14
- [PATCH v5 40/55] tests/tcg/Makefile.target: fix path to config-host.mak, Alex Bennée, 2019/10/14
- [PATCH v5 49/55] accel/stubs: reduce headers from tcg-stub, Alex Bennée, 2019/10/14
- [PATCH v5 43/55] tests/tcg: drop test-i386-fprem from TESTS when not SLOW, Alex Bennée, 2019/10/14