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[PULL 44/68] aspeed/timer: Add support for control register 3
From: |
Peter Maydell |
Subject: |
[PULL 44/68] aspeed/timer: Add support for control register 3 |
Date: |
Mon, 14 Oct 2019 17:03:40 +0100 |
From: Cédric Le Goater <address@hidden>
The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.
The vmstate version is not increased yet because the structure is
modified again in the following patches.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index a791fee276f..1e0288ebc49 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -58,6 +58,7 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
+ uint32_t ctrl3;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
AspeedSCUState *scu;
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index c78bc1bd2d2..d70e78a0293 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -498,6 +498,8 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
switch (offset) {
case 0x38:
+ value = s->ctrl3 & BIT(0);
+ break;
case 0x3C:
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@@ -511,9 +513,24 @@ static uint64_t
aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
uint64_t value)
{
+ const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
+ uint8_t command;
+
switch (offset) {
case 0x38:
+ command = (value >> 1) & 0xFF;
+ if (command == 0xAE) {
+ s->ctrl3 = 0x1;
+ } else if (command == 0xEA) {
+ s->ctrl3 = 0x0;
+ }
+ break;
case 0x3C:
+ if (s->ctrl3 & BIT(0)) {
+ aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
+ }
+ break;
+
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -574,6 +591,7 @@ static void aspeed_timer_reset(DeviceState *dev)
}
s->ctrl = 0;
s->ctrl2 = 0;
+ s->ctrl3 = 0;
}
static const VMStateDescription vmstate_aspeed_timer = {
@@ -597,6 +615,7 @@ static const VMStateDescription vmstate_aspeed_timer_state
= {
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
+ VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
AspeedTimer),
--
2.20.1
- [PULL 32/68] target/arm/arm-semi: Factor out implementation of SYS_WRITE, (continued)
- [PULL 32/68] target/arm/arm-semi: Factor out implementation of SYS_WRITE, Peter Maydell, 2019/10/14
- [PULL 33/68] target/arm/arm-semi: Factor out implementation of SYS_READ, Peter Maydell, 2019/10/14
- [PULL 34/68] target/arm/arm-semi: Factor out implementation of SYS_ISTTY, Peter Maydell, 2019/10/14
- [PULL 35/68] target/arm/arm-semi: Factor out implementation of SYS_SEEK, Peter Maydell, 2019/10/14
- [PULL 36/68] target/arm/arm-semi: Factor out implementation of SYS_FLEN, Peter Maydell, 2019/10/14
- [PULL 37/68] target/arm/arm-semi: Implement support for semihosting feature detection, Peter Maydell, 2019/10/14
- [PULL 38/68] target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension, Peter Maydell, 2019/10/14
- [PULL 39/68] target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension, Peter Maydell, 2019/10/14
- [PULL 40/68] aspeed/wdt: Check correct register for clock source, Peter Maydell, 2019/10/14
- [PULL 41/68] hw/sd/aspeed_sdhci: New device, Peter Maydell, 2019/10/14
- [PULL 44/68] aspeed/timer: Add support for control register 3,
Peter Maydell <=
- [PULL 42/68] hw: aspeed_scu: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 43/68] aspeed/timer: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 45/68] aspeed/timer: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 46/68] aspeed/timer: Add support for IRQ status register on the AST2600, Peter Maydell, 2019/10/14
- [PULL 47/68] aspeed/sdmc: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 48/68] aspeed/sdmc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 50/68] hw: wdt_aspeed: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 49/68] watchdog/aspeed: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 52/68] aspeed/smc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 51/68] aspeed/smc: Introduce segment operations, Peter Maydell, 2019/10/14