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[PATCH v2 18/27] target/riscv: Add Hypervisor trap return support
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v2 18/27] target/riscv: Add Hypervisor trap return support |
|
Date: |
Fri, 25 Oct 2019 16:24:09 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 66 ++++++++++++++++++++++++++++++++--------
1 file changed, 54 insertions(+), 12 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index beb34e705b..e5128570e6 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -73,6 +73,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong
src,
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
+ target_ulong prev_priv, prev_virt, mstatus;
+
if (!(env->priv >= PRV_S)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
@@ -87,16 +89,46 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
- target_ulong mstatus = *env->mstatus;
- target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP);
- mstatus = set_field(mstatus,
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
- MSTATUS_SIE : MSTATUS_UIE << prev_priv,
- get_field(mstatus, MSTATUS_SPIE));
- mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
- mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+ mstatus = *env->mstatus;
+
+ if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
+ /* We support Hypervisor extensions and virtulisation is disabled */
+ target_ulong hstatus = env->hstatus;
+
+ prev_priv = get_field(mstatus, MSTATUS_SPP);
+ prev_virt = get_field(hstatus, HSTATUS_SPV);
+
+ hstatus = set_field(hstatus, HSTATUS_SPV,
+ get_field(hstatus, HSTATUS_SP2V));
+ mstatus = set_field(mstatus, MSTATUS_SPP,
+ get_field(hstatus, HSTATUS_SP2P));
+ hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
+ hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
+ mstatus = set_field(mstatus, SSTATUS_SIE,
+ get_field(mstatus, SSTATUS_SPIE));
+ mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
+
+ *env->mstatus = mstatus;
+ env->hstatus = hstatus;
+
+ if (prev_virt) {
+ riscv_cpu_swap_hypervisor_regs(env);
+ }
+
+ riscv_cpu_set_virt_enabled(env, prev_virt);
+ } else {
+ prev_priv = get_field(mstatus, MSTATUS_SPP);
+
+ mstatus = set_field(mstatus,
+ env->priv_ver >= PRIV_VERSION_1_10_0 ?
+ MSTATUS_SIE : MSTATUS_UIE << prev_priv,
+ get_field(mstatus, MSTATUS_SPIE));
+ mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+ *env->mstatus = mstatus;
+ }
+
riscv_cpu_set_mode(env, prev_priv);
- *env->mstatus = mstatus;
return retpc;
}
@@ -114,14 +146,24 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
target_ulong mstatus = *env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
+ target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_MPIE));
- mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
- mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
- riscv_cpu_set_mode(env, prev_priv);
+ mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
+ mstatus = set_field(mstatus, MSTATUS_MPP, 0);
+ mstatus = set_field(mstatus, MSTATUS_MPV, 0);
*env->mstatus = mstatus;
+ riscv_cpu_set_mode(env, prev_priv);
+
+ if (riscv_has_ext(env, RVH)) {
+ if (prev_virt) {
+ riscv_cpu_swap_hypervisor_regs(env);
+ }
+
+ riscv_cpu_set_virt_enabled(env, prev_virt);
+ }
return retpc;
}
--
2.23.0
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, (continued)
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/10/25
- [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/10/25
- [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/10/25
- [PATCH v2 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/10/25
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/10/25
- [PATCH v2 07/27] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/10/25
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support,
Alistair Francis <=
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/10/25
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/10/25
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/10/25
- [PATCH v2 12/27] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/10/25
- [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/10/25
- [PATCH v2 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/10/25
- [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/10/25
- [PATCH v2 24/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/10/25