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[PULL 18/18] target/riscv: PMP violation due to wrong size parameter
From: |
Palmer Dabbelt |
Subject: |
[PULL 18/18] target/riscv: PMP violation due to wrong size parameter |
Date: |
Mon, 28 Oct 2019 08:49:02 -0700 |
From: Dayeol Lee <address@hidden>
riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation
using pmp_hart_has_privs().
However, if the size is unknown (=0), the ending address will be
`addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`.
This always causes a false PMP violation on the starting address of the
range, as `addr - 1` is not in the range.
In order to fix, we just assume that all bytes from addr to the end of
the page will be accessed if the size is unknown.
Signed-off-by: Dayeol Lee <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/pmp.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d4f1007109..0e6b640fbd 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -223,6 +223,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
{
int i = 0;
int ret = -1;
+ int pmp_size = 0;
target_ulong s = 0;
target_ulong e = 0;
pmp_priv_t allowed_privs = 0;
@@ -232,11 +233,21 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
return true;
}
+ /*
+ * if size is unknown (0), assume that all bytes
+ * from addr to the end of the page will be accessed.
+ */
+ if (size == 0) {
+ pmp_size = -(addr | TARGET_PAGE_MASK);
+ } else {
+ pmp_size = size;
+ }
+
/* 1.10 draft priv spec states there is an implicit order
from low to high */
for (i = 0; i < MAX_RISCV_PMPS; i++) {
s = pmp_is_in_range(env, i, addr);
- e = pmp_is_in_range(env, i, addr + size - 1);
+ e = pmp_is_in_range(env, i, addr + pmp_size - 1);
/* partially inside */
if ((s + e) == 1) {
--
2.21.0
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, (continued)
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, Palmer Dabbelt, 2019/10/28
- [PULL 09/18] riscv/sifive_u: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property, Palmer Dabbelt, 2019/10/28
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28
- [PULL 13/18] riscv/virt: Jump to pflash if specified, Palmer Dabbelt, 2019/10/28
- [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs, Palmer Dabbelt, 2019/10/28
- [PULL 16/18] target/riscv: Make the priv register writable by GDB, Palmer Dabbelt, 2019/10/28
- [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads, Palmer Dabbelt, 2019/10/28
- [PULL 17/18] riscv/boot: Fix possible memory leak, Palmer Dabbelt, 2019/10/28
- [PULL 18/18] target/riscv: PMP violation due to wrong size parameter,
Palmer Dabbelt <=
- Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Peter Maydell, 2019/10/29