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[PULL 1/7] pl031: Expose RTCICR as proper WC register
From: |
Peter Maydell |
Subject: |
[PULL 1/7] pl031: Expose RTCICR as proper WC register |
Date: |
Tue, 19 Nov 2019 13:31:39 +0000 |
From: Alexander Graf <address@hidden>
The current PL031 RTCICR register implementation always clears the
IRQ pending status on a register write, regardless of the value the
guest writes.
To justify that behavior, it references the ARM926EJ-S Development
Chip Reference Manual (DDI0287B) and indicates that said document
states that any write clears the internal IRQ state. It is indeed
true that in section 11.1 this document says:
"The interrupt is cleared by writing any data value to the
interrupt clear register RTCICR".
However, later in section 11.2.2 it contradicts itself by saying:
"Writing 1 to bit 0 of RTCICR clears the RTCINTR flag."
The latter statement matches the PL031 TRM (DDI0224C), which says:
"Writing 1 to bit position 0 clears the corresponding interrupt.
Writing 0 has no effect."
Let's assume that the self-contradictory DDI0287B is in error, and
follow the reference manual for the device itself, by making the
register write-one-to-clear.
Reported-by: Hendrik Borghorst <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Message-id: address@hidden
[PMM: updated commit message to note that DDI0287B says two
conflicting things]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/rtc/pl031.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
index 3a982752a2a..c57cf83165d 100644
--- a/hw/rtc/pl031.c
+++ b/hw/rtc/pl031.c
@@ -149,11 +149,7 @@ static void pl031_write(void * opaque, hwaddr offset,
pl031_update(s);
break;
case RTC_ICR:
- /* The PL031 documentation (DDI0224B) states that the interrupt is
- cleared when bit 0 of the written value is set. However the
- arm926e documentation (DDI0287B) states that the interrupt is
- cleared when any value is written. */
- s->is = 0;
+ s->is &= ~value;
pl031_update(s);
break;
case RTC_CR:
--
2.20.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2019/11/19
- [PULL 1/7] pl031: Expose RTCICR as proper WC register,
Peter Maydell <=
- [PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status, Peter Maydell, 2019/11/19
- [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes, Peter Maydell, 2019/11/19
- [PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller, Peter Maydell, 2019/11/19
- [PULL 5/7] target/arm: Do not reject rt == rt2 for strexd, Peter Maydell, 2019/11/19
- [PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0, Peter Maydell, 2019/11/19
- [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY, Peter Maydell, 2019/11/19
- Re: [PULL 0/7] target-arm queue, Peter Maydell, 2019/11/19