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[PULL 3/4] i386: Add new versions of Skylake/Cascadelake/Icelake without
From: |
Paolo Bonzini |
Subject: |
[PULL 3/4] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX |
Date: |
Thu, 21 Nov 2019 16:36:48 +0100 |
From: Eduardo Habkost <address@hidden>
One of the mitigation methods for TAA[1] is to disable TSX
support on the host system. Linux added a mechanism to disable
TSX globally through the kernel command line, and many Linux
distributions now default to tsx=off. This makes existing CPU
models that have HLE and RTM enabled not usable anymore.
Add new versions of all CPU models that have the HLE and RTM
features enabled, that can be used when TSX is disabled in the
host system.
References:
[1] TAA, TSX asynchronous Abort:
https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort
https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html
Signed-off-by: Eduardo Habkost <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
target/i386/cpu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9cd9adf..37c023f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2902,6 +2902,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { /* end of list */ }
+ }
+ },
{ /* end of list */ }
}
},
@@ -3015,6 +3023,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { /* end of list */ }
+ }
+ },
{ /* end of list */ }
}
},
@@ -3128,6 +3144,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
},
},
+ { .version = 3,
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
@@ -3230,6 +3253,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Icelake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { /* end of list */ }
+ },
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Icelake-Server",
@@ -3334,6 +3369,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { /* end of list */ }
+ },
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Denverton",
--
1.8.3.1
- [PULL 0/4] x86 updates for QEMU 4.2-rc, Paolo Bonzini, 2019/11/21
- [PULL 2/4] target/i386: add support for MSR_IA32_TSX_CTRL, Paolo Bonzini, 2019/11/21
- [PULL 3/4] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX,
Paolo Bonzini <=
- [PULL 4/4] i386: Add -noTSX aliases for hle=off, rtm=off CPU models, Paolo Bonzini, 2019/11/21
- [PULL 1/4] target/i386: add VMX features to named CPU models, Paolo Bonzini, 2019/11/21
- Re: [PULL 0/4] x86 updates for QEMU 4.2-rc, no-reply, 2019/11/21
- Re: [PULL 0/4] x86 updates for QEMU 4.2-rc, Peter Maydell, 2019/11/21