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Re: [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory |
Date: |
Fri, 6 Dec 2019 06:03:46 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 |
On 12/6/19 3:46 AM, Peter Maydell wrote:
>> + case ARMMMUIdx_TagS:
>> + case ARMMMUIdx_TagNS:
>> + /* Indicate tag memory to arm_asidx_from_attrs. */
>> + attrs->target_tlb_bit2 = true;
>> + break;
>
> So here we fall through to the "handle a stage 1 lookup" code, which:
> * sets attrs->secure
> * sets attrs->user (always false, so we could have left it alone)
> * skips the FCSE handling (as we're v8)
> * skips the PMSA handling
> * hits the regime_translation_disabled() check, which fills in
> *phys_ptr, *prot and *page_size and returns
Exactly.
> Maybe it would be clearer if this case here just did all of that:
>
> case ARMMMUIdx_TagS:
> attrs->secure = true;
> /* fall through */
> case ARMMMUIdx_TagNS:
> /* Indicate tag memory to arm_asidx_from_attrs. */
> attrs->target_tlb_bit2 = true;
> *phys_ptr = address;
> *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> *page_size = TARGET_PAGE_SIZE;
> return 0;
>
> Did I miss anything out?
I think that's about it. I thought about doing exactly this.
Also, this is a better location if I ever do something about the TODO in tne
next patch, wherein I talk about mapping not from physical address but from the
normal ram's ramaddr_t, so as to
cache that mapping step as well.
r~