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[PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage t
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails |
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Date: |
Mon, 9 Dec 2019 10:12:04 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8667e5ffce..43c6629014 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -589,16 +589,28 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
}
switch (access_type) {
case MMU_INST_FETCH:
- cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
+ if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
+ } else {
+ cs->exception_index = page_fault_exceptions ?
+ RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
+ }
break;
case MMU_DATA_LOAD:
- cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
+ if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
+ } else {
+ cs->exception_index = page_fault_exceptions ?
+ RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
+ }
break;
case MMU_DATA_STORE:
- cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+ if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
+ } else {
+ cs->exception_index = page_fault_exceptions ?
+ RISCV_EXCP_STORE_PAGE_FAULT :
RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+ }
break;
default:
g_assert_not_reached();
--
2.24.0
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, (continued)
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/12/09
- [PATCH v1 23/36] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/12/09
- [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/12/09
- [PATCH v1 25/36] target/riscv: Add hfence instructions, Alistair Francis, 2019/12/09
- [PATCH v1 26/36] target/riscv: Remove the hret instruction, Alistair Francis, 2019/12/09
- [PATCH v1 27/36] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/12/09
- [PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/12/09
- [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/12/09
- [PATCH v1 30/36] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/12/09
- [PATCH v1 31/36] target/riscv: Implement second stage MMU, Alistair Francis, 2019/12/09
- [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails,
Alistair Francis <=
- [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2019/12/09
- [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/12/09
- [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/12/09
- [PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/12/09
- Re: [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5, Aleksandar Markovic, 2019/12/09