MIPS cache bypass on custom board

[Bensch, Alexander]

Sensitive

Hi all,

Currently stuck on a problem in QEMU 4.0.0. I’m trying to implement a custom device using a MIPS 24Kc CPU. The device boots from an SPI flash device that is mapped to 0x9F000000 (physical address 0x1F000000). I got the initial load and execute working by direct loading a flash dump to a MemoryRegion based at 0x1F000000, which worked great until the ROM needed to access the SPI registers that are addressed to 0xBF000000 (also physical address 0x1F000000). QEMU cannot differentiate reads and writes to 0xBF000000 from reads and writes to 0x9F000000.

 

Initially I assumed this was a caching problem, as I know that the SPI registers are located in the KSEG1 memory segment which uses uncached writes, while the flash mapping is in KSEG0 with cached writes. I also can see that QEMU has logic to handle caching in a few source files within targets/mips/. However, when I read from addresses in the KSEG1 region, I still see contents from the KSEG0 region.

 

My question is whether there is any way to configure a MIPS board such that I can correctly bypass the cache for KSEG1 as expressed by the MIPS documentation?

 

Apologies if details are lacking. Please request more info if needed.

 

Thank you,

Alex Bensch

Performance Testing Engineer
5875 Trinity Parkway, Suite 300

Centreville, Virginia 20120
address@hidden

                  

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