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[PULL 32/34] hw/arm/acpi: enable SHPC native hot plug
From: |
Peter Maydell |
Subject: |
[PULL 32/34] hw/arm/acpi: enable SHPC native hot plug |
Date: |
Mon, 16 Dec 2019 11:09:02 +0000 |
From: Heyi Guo <address@hidden>
After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enable SHPC native
hot plug.
Also update tests/data/acpi/virt/DSDT* to pass "make check".
Cc: Shannon Zhao <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Heyi Guo <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/virt-acpi-build.c | 7 ++++++-
tests/data/acpi/virt/DSDT | Bin 18462 -> 18462 bytes
tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 19799 bytes
tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 18462 bytes
4 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 51b293e0a1e..bd5f771e9be 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -267,7 +267,12 @@ static void acpi_dsdt_add_pci(Aml *scope, const
MemMapEntry *memmap,
aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
- aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1D),
+
+ /*
+ * Allow OS control for all 5 features:
+ * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
+ */
+ aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
aml_name("CTRL")));
ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
index
05bcfc8a912f58f266aa906563ea01c24906717e..d0f3afeb134fdf1c11f64cd06dbcdd30be603b80
100644
GIT binary patch
delta 28
kcmbO?fpOjhMlP3Nmk>D*1_q{tja=*8809zbbW3Ff0C~9xM*si-
delta 28
kcmbO?fpOjhMlP3Nmk>D*1_q|2ja=*87-cu_bW3Ff0C~j-M*si-
diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
index
c041a910fdf272cb89263bb636239ae3a5e1708d..41ccc6431b917252bcbaac86c33b340c796be5ce
100644
GIT binary patch
delta 28
kcmcaUi}Cs_MlP3NmymE@1_mbija=*8809zbbeqQp0Eq|*2mk;8
delta 28
kcmcaUi}Cs_MlP3NmymE@1_ma@ja=*87-cu_beqQp0ErX{2mk;8
diff --git a/tests/data/acpi/virt/DSDT.numamem
b/tests/data/acpi/virt/DSDT.numamem
index
05bcfc8a912f58f266aa906563ea01c24906717e..d0f3afeb134fdf1c11f64cd06dbcdd30be603b80
100644
GIT binary patch
delta 28
kcmbO?fpOjhMlP3Nmk>D*1_q{tja=*8809zbbW3Ff0C~9xM*si-
delta 28
kcmbO?fpOjhMlP3Nmk>D*1_q|2ja=*87-cu_bW3Ff0C~j-M*si-
--
2.20.1
- [PULL 20/34] target/arm: Honor HCR_EL2.TID2 trapping requirements, (continued)
- [PULL 20/34] target/arm: Honor HCR_EL2.TID2 trapping requirements, Peter Maydell, 2019/12/16
- [PULL 21/34] target/arm: Honor HCR_EL2.TID1 trapping requirements, Peter Maydell, 2019/12/16
- [PULL 22/34] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions, Peter Maydell, 2019/12/16
- [PULL 23/34] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2, Peter Maydell, 2019/12/16
- [PULL 24/34] target/arm: Add support for missing Jazelle system registers, Peter Maydell, 2019/12/16
- [PULL 25/34] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on(), Peter Maydell, 2019/12/16
- [PULL 26/34] tcg: cputlb: Add probe_read, Peter Maydell, 2019/12/16
- [PULL 28/34] migration: ram: Switch to ram block writeback, Peter Maydell, 2019/12/16
- [PULL 29/34] target/arm: Add support for DC CVAP & DC CVADP ins, Peter Maydell, 2019/12/16
- [PULL 30/34] hw/arm/sbsa-ref: Simplify by moving the gic in the machine state, Peter Maydell, 2019/12/16
- [PULL 32/34] hw/arm/acpi: enable SHPC native hot plug,
Peter Maydell <=
- [PULL 27/34] Memory: Enable writeback for given memory region, Peter Maydell, 2019/12/16
- [PULL 31/34] hw/arm/acpi: simplify AML bit and/or statement, Peter Maydell, 2019/12/16
- [PULL 34/34] target/arm: ensure we use current exception state after SCR update, Peter Maydell, 2019/12/16
- [PULL 33/34] hw/arm/virt: Simplify by moving the gic in the machine state, Peter Maydell, 2019/12/16
- Re: [PULL 00/34] target-arm queue, Peter Maydell, 2019/12/16