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[PATCH v39 09/22] target/avr: Add instruction translation - MCU Control
From: |
Michael Rolnik |
Subject: |
[PATCH v39 09/22] target/avr: Add instruction translation - MCU Control Instructions |
Date: |
Wed, 18 Dec 2019 23:03:16 +0200 |
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik <address@hidden>
---
target/avr/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index e303a1f4cc..46cbcc9305 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2606,3 +2606,71 @@ static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
return true;
}
+
+/*
+ * MCU Control Instructions
+ */
+
+/*
+ * The BREAK instruction is used by the On-chip Debug system, and is
+ * normally not used in the application software. When the BREAK instruction
is
+ * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
+ * Debugger access to internal resources. If any Lock bits are set, or either
+ * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
+ * instruction as a NOP and will not enter the Stopped mode. This instruction
+ * is not available in all devices. Refer to the device specific instruction
+ * set summary.
+ */
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
+{
+ if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
+ return true;
+ }
+
+#ifdef BREAKPOINT_ON_BREAK
+ tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
+ gen_helper_debug(cpu_env);
+ ctx->bstate = DISAS_EXIT;
+#else
+ /* NOP */
+#endif
+
+ return true;
+}
+
+
+/*
+ * This instruction performs a single cycle No Operation.
+ */
+static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
+{
+
+ /* NOP */
+
+ return true;
+}
+
+
+/*
+ * This instruction sets the circuit in sleep mode defined by the MCU
+ * Control Register.
+ */
+static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
+{
+ gen_helper_sleep(cpu_env);
+ ctx->bstate = DISAS_NORETURN;
+ return true;
+}
+
+
+/*
+ * This instruction resets the Watchdog Timer. This instruction must be
+ * executed within a limited time given by the WD prescaler. See the Watchdog
+ * Timer hardware specification.
+ */
+static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
+{
+ gen_helper_wdr(cpu_env);
+
+ return true;
+}
--
2.17.2 (Apple Git-113)
- [PATCH v39 00/22] QEMU AVR 8 bit cores, Michael Rolnik, 2019/12/18
- [PATCH v39 06/22] target/avr: Add instruction translation - Branch Instructions, Michael Rolnik, 2019/12/18
- [PATCH v39 08/22] target/avr: Add instruction translation - Bit and Bit-test Instructions, Michael Rolnik, 2019/12/18
- [PATCH v39 07/22] target/avr: Add instruction translation - Data Transfer Instructions, Michael Rolnik, 2019/12/18
- [PATCH v39 09/22] target/avr: Add instruction translation - MCU Control Instructions,
Michael Rolnik <=
- [PATCH v39 10/22] target/avr: Add instruction translation - CPU main translation function, Michael Rolnik, 2019/12/18
- [PATCH v39 11/22] target/avr: Add instruction disassembly function, Michael Rolnik, 2019/12/18
- [PATCH v39 14/22] target/avr: Add dummy mask device, Michael Rolnik, 2019/12/18
- [PATCH v39 13/22] target/avr: Add limited support for 16 bit timer peripheral, Michael Rolnik, 2019/12/18
- [PATCH v39 12/22] target/avr: Add limited support for USART peripheral, Michael Rolnik, 2019/12/18
- [PATCH v39 15/22] target/avr: Add example board configuration, Michael Rolnik, 2019/12/18