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[PATCH v4 14/21] target/arm: don't bother with id_aa64pfr0_read for USER
From: |
Alex Bennée |
Subject: |
[PATCH v4 14/21] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY |
Date: |
Fri, 20 Dec 2019 12:04:31 +0000 |
For system emulation we need to check the state of the GIC before we
report the value. However this isn't relevant to exporting of the
value to linux-user and indeed breaks the exported value as set by
modify_arm_cp_regs.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
v2
- extend the ifdef and make type CONST with no accessfn
---
target/arm/helper.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 857581feba4..23de21f8820 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5912,6 +5912,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const
ARMCPRegInfo *ri)
return pfr1;
}
+#ifndef CONFIG_USER_ONLY
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
@@ -5922,6 +5923,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
return pfr0;
}
+#endif
/* Shared logic between LORID and the rest of the LOR* registers.
* Secure state has already been delt with.
@@ -6414,16 +6416,24 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* define new registers here.
*/
ARMCPRegInfo v8_idregs[] = {
- /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
- * know the right value for the GIC field until after we
- * define these regs.
+ /*
+ * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
+ * emulation because we don't know the right value for the
+ * GIC field until after we define these regs.
*/
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_NO_RAW,
+ .access = PL1_R,
+#ifdef CONFIG_USER_ONLY
+ .type = ARM_CP_CONST,
+ .resetvalue = cpu->isar.id_aa64pfr0
+#else
+ .type = ARM_CP_NO_RAW,
.accessfn = access_aa64_tid3,
.readfn = id_aa64pfr0_read,
- .writefn = arm_cp_write_ignore },
+ .writefn = arm_cp_write_ignore
+#endif
+ },
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
--
2.20.1
- [PATCH v4 10/21] target/arm: explicitly encode regnum in our XML, (continued)
- [PATCH v4 10/21] target/arm: explicitly encode regnum in our XML, Alex Bennée, 2019/12/20
- [PATCH v4 09/21] target/arm: prepare for multiple dynamic XMLs, Alex Bennée, 2019/12/20
- [PATCH v4 17/21] tests/tcg/aarch64: add a gdbstub testcase for SVE registers, Alex Bennée, 2019/12/20
- [PATCH v4 16/21] tests/guest-debug: add a simple test runner, Alex Bennée, 2019/12/20
- [PATCH v4 08/21] gdbstub: extend GByteArray to read register helpers, Alex Bennée, 2019/12/20
- [PATCH v4 18/21] tests/tcg/aarch64: add SVE iotcl test, Alex Bennée, 2019/12/20
- [PATCH v4 11/21] target/arm: default SVE length to 64 bytes for linux-user, Alex Bennée, 2019/12/20
- [PATCH v4 12/21] target/arm: generate xml description of our SVE registers, Alex Bennée, 2019/12/20
- [PATCH v4 15/21] tests/tcg/aarch64: userspace system register test, Alex Bennée, 2019/12/20
- [PATCH v4 14/21] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY,
Alex Bennée <=
- [PATCH v4 13/21] tests/tcg: add a configure compiler check for ARMv8.1 and SVE, Alex Bennée, 2019/12/20
- [PATCH v4 19/21] tests/tcg/aarch64: add test-sve-ioctl guest-debug test, Alex Bennée, 2019/12/20
- [PATCH v4 21/21] gdbstub: do not split gdb_monitor_write payload, Alex Bennée, 2019/12/20
- [PATCH v4 20/21] gdbstub: change GDBState.last_packet to GByteArray, Alex Bennée, 2019/12/20