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[PULL 06/12] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value
From: |
Peter Maydell |
Subject: |
[PULL 06/12] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value |
Date: |
Fri, 20 Dec 2019 14:26:38 +0000 |
From: Simon Veith <address@hidden>
There are two issues with the current value of SMMU_BASE_ADDR_MASK:
- At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec,
we should also be treating bit 5 as zero in the base address.
- At the upper end, we are clearing bits [63:48]. Per the SMMUv3 spec,
only bits [63:52] must be explicitly treated as zero.
Update the SMMU_BASE_ADDR_MASK value to mask out bits [63:52] and [5:0].
ref. ARM IHI 0070C, section 6.3.23.
Signed-off-by: Simon Veith <address@hidden>
Acked-by: Eric Auger <address@hidden>
Tested-by: Eric Auger <address@hidden>
Message-id: address@hidden
Cc: Eric Auger <address@hidden>
Cc: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/smmuv3-internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index d190181ef1b..042b4358084 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -99,7 +99,7 @@ REG32(GERROR_IRQ_CFG2, 0x74)
#define A_STRTAB_BASE 0x80 /* 64b */
-#define SMMU_BASE_ADDR_MASK 0xffffffffffe0
+#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0
REG32(STRTAB_BASE_CFG, 0x88)
FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
--
2.20.1
- [PULL 00/12] target-arm queue, Peter Maydell, 2019/12/20
- [PULL 01/12] target/arm: Remove redundant scaling of nexttick, Peter Maydell, 2019/12/20
- [PULL 02/12] target/arm: Abstract the generic timer frequency, Peter Maydell, 2019/12/20
- [PULL 03/12] target/arm: Prepare generic timer for per-platform CNTFRQ, Peter Maydell, 2019/12/20
- [PULL 04/12] ast2600: Configure CNTFRQ at 1125MHz, Peter Maydell, 2019/12/20
- [PULL 05/12] hw/arm/smmuv3: Apply address mask to linear strtab base address, Peter Maydell, 2019/12/20
- [PULL 06/12] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value,
Peter Maydell <=
- [PULL 07/12] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE, Peter Maydell, 2019/12/20
- [PULL 08/12] hw/arm/smmuv3: Align stream table base address to table size, Peter Maydell, 2019/12/20
- [PULL 09/12] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro, Peter Maydell, 2019/12/20
- [PULL 10/12] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position, Peter Maydell, 2019/12/20
- [PULL 11/12] target/arm: Display helpful message when hflags mismatch, Peter Maydell, 2019/12/20
- [PULL 12/12] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on(), Peter Maydell, 2019/12/20