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Re: [PATCH v2 24/28] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MOD
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From: |
Alex Bennée |
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Subject: |
Re: [PATCH v2 24/28] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX |
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Date: |
Fri, 20 Dec 2019 19:37:53 +0000 |
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User-agent: |
mu4e 1.3.5; emacs 27.0.50 |
Richard Henderson <address@hidden> writes:
> The separate suffixed functions were used to construct
> some do_##insn function switched on mmu_idx. The interface
> is exactly identical to the *_mmuidx_ra functions. Replace
> them directly and remove the constructions.
>
> Cc: Aurelien Jarno <address@hidden>
> Cc: Aleksandar Rikalo <address@hidden>
> Reviewed-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/mips/cpu.h | 4 -
> target/mips/op_helper.c | 182 +++++++++++++---------------------------
> 2 files changed, 60 insertions(+), 126 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index ca00f41daf..c218ccc4a8 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1147,10 +1147,6 @@ extern uint32_t cpu_rddsp(uint32_t mask_num,
> CPUMIPSState *env);
> * MMU modes definitions. We carefully match the indices with our
> * hflags layout.
> */
> -#define MMU_MODE0_SUFFIX _kernel
> -#define MMU_MODE1_SUFFIX _super
> -#define MMU_MODE2_SUFFIX _user
> -#define MMU_MODE3_SUFFIX _error
> #define MMU_USER_IDX 2
>
> static inline int hflags_mmu_index(uint32_t hflags)
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 18fcee4a78..79d44da6fa 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -52,69 +52,6 @@ static void raise_exception(CPUMIPSState *env, uint32_t
> exception)
> do_raise_exception(env, exception, 0);
> }
>
> -#if defined(CONFIG_USER_ONLY)
> -#define HELPER_LD(name, insn, type) \
> -static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
> - int mem_idx, uintptr_t retaddr) \
> -{ \
> - return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
> -}
> -#else
> -#define HELPER_LD(name, insn, type) \
> -static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
> - int mem_idx, uintptr_t retaddr) \
> -{ \
> - switch (mem_idx) { \
> - case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
> - case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
> - default: \
> - case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
> - case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
> - } \
> -}
> -#endif
> -HELPER_LD(lw, ldl, int32_t)
> -#if defined(TARGET_MIPS64)
> -HELPER_LD(ld, ldq, int64_t)
> -#endif
> -#undef HELPER_LD
> -
> -#if defined(CONFIG_USER_ONLY)
> -#define HELPER_ST(name, insn, type) \
> -static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
> - type val, int mem_idx, uintptr_t retaddr) \
> -{ \
> - cpu_##insn##_data_ra(env, addr, val, retaddr); \
> -}
> -#else
> -#define HELPER_ST(name, insn, type) \
> -static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
> - type val, int mem_idx, uintptr_t retaddr) \
> -{ \
> - switch (mem_idx) { \
> - case 0: \
> - cpu_##insn##_kernel_ra(env, addr, val, retaddr); \
> - break; \
> - case 1: \
> - cpu_##insn##_super_ra(env, addr, val, retaddr); \
> - break; \
> - default: \
> - case 2: \
> - cpu_##insn##_user_ra(env, addr, val, retaddr); \
> - break; \
> - case 3: \
> - cpu_##insn##_error_ra(env, addr, val, retaddr); \
> - break; \
> - } \
> -}
> -#endif
> -HELPER_ST(sb, stb, uint8_t)
> -HELPER_ST(sw, stl, uint32_t)
> -#if defined(TARGET_MIPS64)
> -HELPER_ST(sd, stq, uint64_t)
> -#endif
> -#undef HELPER_ST
> -
> /* 64 bits arithmetic for 32 bits hosts */
> static inline uint64_t get_HILO(CPUMIPSState *env)
> {
> @@ -379,12 +316,12 @@ target_ulong helper_##name(CPUMIPSState *env,
> target_ulong arg, int mem_idx) \
> }
> \
> env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC());
> \
> env->lladdr = arg;
> \
> - env->llval = do_##insn(env, arg, mem_idx, GETPC());
> \
> + env->llval = cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC());
> \
> return env->llval;
> \
> }
> -HELPER_LD_ATOMIC(ll, lw, 0x3)
> +HELPER_LD_ATOMIC(ll, ldl, 0x3)
> #ifdef TARGET_MIPS64
> -HELPER_LD_ATOMIC(lld, ld, 0x7)
> +HELPER_LD_ATOMIC(lld, ldq, 0x7)
> #endif
> #undef HELPER_LD_ATOMIC
> #endif
> @@ -400,42 +337,42 @@ HELPER_LD_ATOMIC(lld, ld, 0x7)
> void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
> int mem_idx)
> {
> - do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
> + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
>
> if (GET_LMASK(arg2) <= 2) {
> - do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK(arg2) <= 1) {
> - do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK(arg2) == 0) {
> - do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
> + mem_idx, GETPC());
> }
> }
>
> void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
> int mem_idx)
> {
> - do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
> + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
>
> if (GET_LMASK(arg2) >= 1) {
> - do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK(arg2) >= 2) {
> - do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK(arg2) == 3) {
> - do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
> + mem_idx, GETPC());
> }
> }
>
> @@ -453,82 +390,82 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1,
> target_ulong arg2,
> void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
> int mem_idx)
> {
> - do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
> + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
>
> if (GET_LMASK64(arg2) <= 6) {
> - do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) <= 5) {
> - do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) <= 4) {
> - do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) <= 3) {
> - do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) <= 2) {
> - do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) <= 1) {
> - do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) <= 0) {
> - do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
> + mem_idx, GETPC());
> }
> }
>
> void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
> int mem_idx)
> {
> - do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
> + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
>
> if (GET_LMASK64(arg2) >= 1) {
> - do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) >= 2) {
> - do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) >= 3) {
> - do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) >= 4) {
> - do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) >= 5) {
> - do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) >= 6) {
> - do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
> + mem_idx, GETPC());
> }
>
> if (GET_LMASK64(arg2) == 7) {
> - do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
> - GETPC());
> + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
> + mem_idx, GETPC());
> }
> }
> #endif /* TARGET_MIPS64 */
> @@ -546,14 +483,14 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr,
> target_ulong reglist,
>
> for (i = 0; i < base_reglist; i++) {
> env->active_tc.gpr[multiple_regs[i]] =
> - (target_long)do_lw(env, addr, mem_idx, GETPC());
> + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
> addr += 4;
> }
> }
>
> if (do_r31) {
> - env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
> - GETPC());
> + env->active_tc.gpr[31] =
> + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
> }
> }
>
> @@ -567,14 +504,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr,
> target_ulong reglist,
> target_ulong i;
>
> for (i = 0; i < base_reglist; i++) {
> - do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
> - GETPC());
> + cpu_stw_mmuidx_ra(env, addr,
> env->active_tc.gpr[multiple_regs[i]],
> + mem_idx, GETPC());
> addr += 4;
> }
> }
>
> if (do_r31) {
> - do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
> + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx,
> GETPC());
> }
> }
>
> @@ -589,14 +526,15 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr,
> target_ulong reglist,
> target_ulong i;
>
> for (i = 0; i < base_reglist; i++) {
> - env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
> - GETPC());
> + env->active_tc.gpr[multiple_regs[i]] =
> + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
> addr += 8;
> }
> }
>
> if (do_r31) {
> - env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
> + env->active_tc.gpr[31] =
> + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
> }
> }
>
> @@ -610,14 +548,14 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr,
> target_ulong reglist,
> target_ulong i;
>
> for (i = 0; i < base_reglist; i++) {
> - do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
> - GETPC());
> + cpu_stq_mmuidx_ra(env, addr,
> env->active_tc.gpr[multiple_regs[i]],
> + mem_idx, GETPC());
> addr += 8;
> }
> }
>
> if (do_r31) {
> - do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
> + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx,
> GETPC());
> }
> }
> #endif
--
Alex Bennée
- Re: [PATCH v2 19/28] target/microblaze: Remove MMU_MODE{0, 1, 2}_SUFFIX, (continued)
- [PATCH v2 20/28] target/sh4: Remove MMU_MODE{0,1}_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 21/28] target/unicore32: Remove MMU_MODE{0,1}_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 22/28] target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 23/28] target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0, 1}_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 24/28] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX, Richard Henderson, 2019/12/16
- Re: [PATCH v2 24/28] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX,
Alex Bennée <=
- [PATCH v2 25/28] target/s390x: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 26/28] target/ppc: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 27/28] cputlb: Remove support for MMU_MODE*_SUFFIX, Richard Henderson, 2019/12/16
- [PATCH v2 28/28] cputlb: Expand cpu_ldst_template.h in cputlb.c, Richard Henderson, 2019/12/16