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[PULL 22/38] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPAB
From: |
Paolo Bonzini |
Subject: |
[PULL 22/38] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES |
Date: |
Wed, 8 Jan 2020 13:32:39 +0100 |
From: Xiaoyao Li <address@hidden>
The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
for some security issues. Add the definitions for them to be used by named
CPU models.
Signed-off-by: Xiaoyao Li <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
target/i386/cpu.h | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index af28293..594326a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -835,12 +835,15 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
/* MSR Feature Bits */
-#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
-#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
-#define MSR_ARCH_CAP_RSBA (1U << 2)
+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
+#define MSR_ARCH_CAP_RSBA (1U << 2)
#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
-#define MSR_ARCH_CAP_SSB_NO (1U << 4)
-#define MSR_ARCH_CAP_MDS_NO (1U << 5)
+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
+#define MSR_ARCH_CAP_MDS_NO (1U << 5)
+#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
+#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
+#define MSR_ARCH_CAP_TAA_NO (1U << 8)
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
--
1.8.3.1
- [PULL 12/38] hw/ppc/Kconfig: Restrict the MPC I2C controller to e500-based platforms, (continued)
- [PULL 12/38] hw/ppc/Kconfig: Restrict the MPC I2C controller to e500-based platforms, Paolo Bonzini, 2020/01/08
- [PULL 13/38] hw/ppc/Kconfig: Let the Sam460ex board use the PowerPC 405 devices, Paolo Bonzini, 2020/01/08
- [PULL 14/38] hw/ppc/Kconfig: Let the Xilinx Virtex5 ML507 use the PPC-440 devices, Paolo Bonzini, 2020/01/08
- [PULL 15/38] hw/ppc/Makefile: Simplify the sPAPR PCI objects rule, Paolo Bonzini, 2020/01/08
- [PULL 16/38] hw/ppc/Kconfig: Only select fw_cfg with machines using OpenBIOS, Paolo Bonzini, 2020/01/08
- [PULL 17/38] hw/ppc/Kconfig: Only select FDT helper for machines using it, Paolo Bonzini, 2020/01/08
- [PULL 19/38] hw/nvram/Kconfig: Restrict CHRP NVRAM to machines using OpenBIOS or SLOF, Paolo Bonzini, 2020/01/08
- [PULL 18/38] hw/nvram/Kconfig: Add an entry for the NMC93xx EEPROM, Paolo Bonzini, 2020/01/08
- [PULL 20/38] hw/rtc/mc146818: Add missing dependency on ISA Bus, Paolo Bonzini, 2020/01/08
- [PULL 21/38] target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub, Paolo Bonzini, 2020/01/08
- [PULL 22/38] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES,
Paolo Bonzini <=
- [PULL 23/38] target/i386: Add missed features to Cooperlake CPU model, Paolo Bonzini, 2020/01/08
- [PULL 25/38] hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 24/38] hw/ipmi: Remove unnecessary declarations, Paolo Bonzini, 2020/01/08
- [PULL 26/38] hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 27/38] hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 28/38] hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 29/38] ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 30/38] vhost-user-crypto: Explicit we ignore some QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 31/38] vhost-user-net: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 32/38] vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08