Re: [PATCH] docs: qemu-cpu-models: Document '-noTSX' variants and 'mds-no'

[Kashyap Chamarthy]

On Thu, Jan 16, 2020 at 06:36:38PM +0100, Kashyap Chamarthy wrote:

[...]

>   (2) There are _three_ variants[+] of CascadeLake CPUs, with different
>       stepping levels: 5, 6, and 7.  To quite wikichip.org[*]:

s/quite/quote/

> 
>         "note that while steppings 6 & 7 are fully mitigated, earlier
>         stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM"
> 
>       The above is also indicated in the Intel's manual itself[+], as
>       indicated by "No" under the three columns of MFBDS, MSBDS, and
>       MLPDS.
> 
>       [+] 
> https://software.intel.com/security-software-guidance/insights/processors-affected-microarchitectural-data-sampling
>       [*] 
> https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake#Key_changes_from_Skylake
> 
> Signed-off-by: Kashyap Chamarthy <address@hidden>
> ---
> TODO:
>  - I think I also need to add a note about 'tsx-ctrl' bit.  Here too,
>    same question as above -- does it show up in /proc/cpuinfo/?

While at it ... if I mention 'mds-no', then it would be inconsistent,
and inaccurate, if I don't also mention 'taa-no' IA32_ARCH_CAPABILITIES
MSR bit.

In short, I should mention the following MSR bits, and their use, in
context:

  - mds-no
  - taa-no
  - tsx-ctrl

... while bearing in mind that none (?) of these MSR bits will show up
under /proc/cpuinfo in the guest, rather they're used to populate the
relevant vulnerability file in sysfs
(/sys/devices/system/cpu/vulnerabilities/).


[...]

-- 
/kashyap