qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] riscv: Add semihosting support [v4]


From: Jonathan Behrens
Subject: Re: [PATCH] riscv: Add semihosting support [v4]
Date: Wed, 29 Jan 2020 13:06:11 -0500

The text you are referencing (the couple italic paragraphs below section 2.8 in the unprivileged ISA) is non-normative and "can be skipped if the reader is only interested in the specification itself". This convention of making indented italic text non-normative is described at the bottom of page 1 of the linked document.

Jonathan

On Wed, Jan 29, 2020 at 11:45 AM Keith Packard via <address@hidden> wrote:
Peter Maydell <address@hidden> writes:

> True but irrelevant. You need to refer to a proper
> risc-v specification for your semihosting.

The RISC-V Foundation defined semihosting as relative to the existing
ARM specification, so using a link to that is appropriate here.

Here's the current specification of the unprivileged ISA, which includes
the definition of semihosting

        https://riscv.org/specifications/

While it may be nice in some abstract sense to create a "better"
semihosting spec, that's not what the RISC-V foundation has decided to
do.

--
-keith

reply via email to

[Prev in Thread] Current Thread [Next in Thread]