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[PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE
From: |
Richard Henderson |
Subject: |
[PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE |
Date: |
Wed, 29 Jan 2020 15:55:54 -0800 |
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v4: Consistently check E2H & TGE & ELUsingAArch32(EL2).
Do not apply TGE at EL2.
---
target/arm/helper.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index aba79db2a1..128a400011 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11317,12 +11317,16 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
+ /* See ARM pseudo-function ELIsInHost. */
switch (el) {
case 0:
- /* TODO: ARMv8.1-VHE */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdx_SE10_0;
}
+ if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)
+ && arm_el_is_aa64(env, 2)) {
+ return ARMMMUIdx_E20_0;
+ }
return ARMMMUIdx_E10_0;
case 1:
if (arm_is_secure_below_el3(env)) {
@@ -11330,8 +11334,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
}
return ARMMMUIdx_E10_1;
case 2:
- /* TODO: ARMv8.1-VHE */
/* TODO: ARMv8.4-SecEL2 */
+ /* Note that TGE does not apply at EL2. */
+ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) {
+ return ARMMMUIdx_E20_2;
+ }
return ARMMMUIdx_E2;
case 3:
return ARMMMUIdx_SE3;
--
2.20.1
- [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], (continued)
- [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], Richard Henderson, 2020/01/29
- [PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2020/01/29
- [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2020/01/29
- [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs, Richard Henderson, 2020/01/29
- [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit, Richard Henderson, 2020/01/29
- [PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2020/01/29
- [PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2020/01/29
- [PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2020/01/29
- [PATCH v5 20/41] target/arm: Add regime_has_2_ranges, Richard Henderson, 2020/01/29
- [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE,
Richard Henderson <=
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/01/29
- [PATCH v5 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/01/29
- [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/01/29