Re: [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime

[Peter Maydell]

On Sat, 1 Feb 2020 at 19:29, Richard Henderson
<address@hidden> wrote:
>
> Reviewed-by: Peter Maydell <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> v5: Flush all EL2 regimes with TLBI ALLE2 (pmm).
> ---
>  target/arm/helper.c | 34 +++++++++++++++++++++++++++-------
>  1 file changed, 27 insertions(+), 7 deletions(-)

> +static int vae2_tlbmask(CPUARMState *env)
> +{
> +    if (arm_hcr_el2_eff(env) & HCR_E2H) {
> +        return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2;
> +    } else {
> +        return ARMMMUIdxBit_E2;
> +    }
> +}

The TLBI VAE2 docs say the TLB entry has to be invalidated if:
 * The entry would be required to translate the specified VA using
   the EL2 or the EL2&0 translation regime.

and this isn't conditional on whether HCR_EL2.E2H is 0 or 1.
So given that we don't flush all TLBs when E2H is changed,
I think we need to always flush all of
 ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2
here.

That would make this the same as alle2_tlbmask, which
seems logically correct, since the difference between
TLBI VAE2 and TLBI_ALLE2 is that the former specifies
a VA+ASID (and the ASID should matter if E2H==1 and
be ignored if E2H==0), not which translation regimes
they affect. e2_tlbmask() is probably a better name than
alle2_tlbmask(), in that case.

thanks
-- PMM