[PATCH v3 09/20] target/arm: Tidy msr_mask

[Richard Henderson]

The CPSR_USER mask for IS_USER already avoids all of the RES0
bits as per aarch32_cpsr_valid_mask.  Fix up the formatting.

Signed-off-by: Richard Henderson <address@hidden>
---
 target/arm/translate.c | 42 ++++++++++++++++++++++++------------------
 1 file changed, 24 insertions(+), 18 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 032f7074cb..2b3bfcf7ca 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2734,28 +2734,34 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, 
int x, int y)
 /* Return the mask of PSR bits set by a MSR instruction.  */
 static uint32_t msr_mask(DisasContext *s, int flags, int spsr)
 {
-    uint32_t mask;
+    uint32_t mask = 0;
 
-    mask = 0;
-    if (flags & (1 << 0))
+    if (flags & (1 << 0)) {
         mask |= 0xff;
-    if (flags & (1 << 1))
-        mask |= 0xff00;
-    if (flags & (1 << 2))
-        mask |= 0xff0000;
-    if (flags & (1 << 3))
-        mask |= 0xff000000;
-
-    /* Mask out undefined bits.  */
-    mask &= aarch32_cpsr_valid_mask(s->features, s->isar);
-
-    /* Mask out execution state and reserved bits.  */
-    if (!spsr) {
-        mask &= ~CPSR_EXEC;
     }
-    /* Mask out privileged bits.  */
-    if (IS_USER(s))
+    if (flags & (1 << 1)) {
+        mask |= 0xff00;
+    }
+    if (flags & (1 << 2)) {
+        mask |= 0xff0000;
+    }
+    if (flags & (1 << 3)) {
+        mask |= 0xff000000;
+    }
+
+    if (IS_USER(s)) {
+        /* Mask out privileged bits.  */
         mask &= CPSR_USER;
+    } else {
+        /* Mask out undefined bits.  */
+        mask &= aarch32_cpsr_valid_mask(s->features, s->isar);
+
+        /* Mask out execution state and reserved bits.  */
+        if (!spsr) {
+            mask &= ~CPSR_EXEC;
+        }
+    }
+
     return mask;
 }
 
-- 
2.20.1