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[PATCH v7 23/41] target/arm: Update aa64_zva_access for EL2
From: |
Richard Henderson |
Subject: |
[PATCH v7 23/41] target/arm: Update aa64_zva_access for EL2 |
Date: |
Thu, 6 Feb 2020 10:54:30 +0000 |
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e4f368d96b..e41bece6b5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4159,11 +4159,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
- /* We don't implement EL2, so the only control on DC ZVA is the
- * bit in the SCTLR which can prohibit access for EL0.
- */
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
- return CP_ACCESS_TRAP;
+ int cur_el = arm_current_el(env);
+
+ if (cur_el < 2) {
+ uint64_t hcr = arm_hcr_el2_eff(env);
+
+ if (cur_el == 0) {
+ if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+ if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
+ return CP_ACCESS_TRAP;
+ }
+ if (hcr & HCR_TDZ) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ } else if (hcr & HCR_TDZ) {
+ return CP_ACCESS_TRAP_EL2;
+ }
}
return CP_ACCESS_OK;
}
--
2.20.1
- [PATCH v7 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, (continued)
- [PATCH v7 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2020/02/06
- [PATCH v7 07/41] target/arm: Split out alle1_tlbmask, Richard Henderson, 2020/02/06
- [PATCH v7 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], Richard Henderson, 2020/02/06
- [PATCH v7 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2020/02/06
- [PATCH v7 15/41] target/arm: Recover 4 bits from TBFLAGs, Richard Henderson, 2020/02/06
- [PATCH v7 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2020/02/06
- [PATCH v7 17/41] target/arm: Rearrange ARMMMUIdxBit, Richard Henderson, 2020/02/06
- [PATCH v7 20/41] target/arm: Add regime_has_2_ranges, Richard Henderson, 2020/02/06
- [PATCH v7 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/02/06
- [PATCH v7 19/41] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2020/02/06
- [PATCH v7 23/41] target/arm: Update aa64_zva_access for EL2,
Richard Henderson <=
- [PATCH v7 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/02/06
- [PATCH v7 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/02/06
- [PATCH v7 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/02/06
- [PATCH v7 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/02/06
- [PATCH v7 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/02/06
- [PATCH v7 39/41] target/arm: Pass more cpu state to arm_excp_unmasked, Richard Henderson, 2020/02/06
- [PATCH v7 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 38/41] target/arm: Move arm_excp_unmasked to cpu.c, Richard Henderson, 2020/02/06