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[PATCH v4 00/20] target/arm: Implement PAN, ATS1E1, UAO

From: Richard Henderson
Subject: [PATCH v4 00/20] target/arm: Implement PAN, ATS1E1, UAO
Date: Sat, 8 Feb 2020 12:57:56 +0000


Version 4 incorporates the feedback on v3.  In particular:
  * Split out CPSR_J masking to its own patch.
  * Merge trivial braces formatting fixes into patch 5.
  * Drop "Tidy msr_mask" patch, leaving CPSR_USER handling alone.
  * Fixes for EL3 in "Set PAN bit as required on exception entry".

Patches without review:



Richard Henderson (20):
  target/arm: Add arm_mmu_idx_is_stage1_of_2
  target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled
  target/arm: Add isar_feature tests for PAN + ATS1E1
  target/arm: Move LOR regdefs to file scope
  target/arm: Split out aarch32_cpsr_valid_mask
  target/arm: Mask CPSR_J when Jazelle is not enabled
  target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask
  target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return
  target/arm: Remove CPSR_RESERVED
  target/arm: Introduce aarch64_pstate_valid_mask
  target/arm: Update MSR access for PAN
  target/arm: Update arm_mmu_idx_el for PAN
  target/arm: Enforce PAN semantics in get_S1prot
  target/arm: Set PAN bit as required on exception entry
  target/arm: Implement ATS1E1 system registers
  target/arm: Enable ARMv8.2-ATS1E1 in -cpu max
  target/arm: Add ID_AA64MMFR2_EL1
  target/arm: Update MSR access to UAO
  target/arm: Implement UAO semantics
  target/arm: Enable ARMv8.2-UAO in -cpu max

 target/arm/cpu-param.h     |   2 +-
 target/arm/cpu.h           |  95 ++++++++---
 target/arm/internals.h     |  85 ++++++++++
 target/arm/cpu.c           |   4 +
 target/arm/cpu64.c         |   9 +
 target/arm/helper-a64.c    |   6 +-
 target/arm/helper.c        | 327 +++++++++++++++++++++++++++++--------
 target/arm/kvm64.c         |   2 +
 target/arm/op_helper.c     |  14 +-
 target/arm/translate-a64.c |  31 ++++
 target/arm/translate.c     |  42 +++--
 11 files changed, 499 insertions(+), 118 deletions(-)


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