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Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2
From: |
Bin Meng |
Subject: |
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2 |
Date: |
Thu, 13 Feb 2020 20:30:32 +0800 |
Hi Palmer,
On Thu, Feb 13, 2020 at 1:30 AM Palmer Dabbelt <address@hidden> wrote:
>
> The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2020-02-10 17:08:51 +0000)
>
> are available in the Git repository at:
>
> address@hidden:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf2
>
> for you to fetch changes up to 9c8fdcece53e05590441785ab22d91a22da36e29:
>
> MAINTAINERS: Add maintainer entry for Goldfish RTC (2020-02-10 12:01:39
> -0800)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 2
>
> This is a fairly light-weight pull request, but I wanted to send it out to
> avoid the Goldfish stuff getting buried as the next PR should contain the H
> extension implementation.
>
> As far as this PR goes, it contains:
>
> * The addition of syscon device tree nodes for reboot and poweroff, which
> allows Linux to control QEMU without an additional driver. The existing
> device was already compatible with the syscon interface.
> * A fix to our GDB stub to avoid confusing XLEN and FLEN, specifically useful
> for rv32id-based systems.
> * A device emulation for the Goldfish RTC device, a simple memory-mapped RTC.
> * The addition of the Goldfish RTC device to the RISC-V virt board.
>
> This passes "make check" and boots buildroot for me.
>
This PR is still missing: http://patchwork.ozlabs.org/patch/1199516/
> ----------------------------------------------------------------
>
> Peter: I'm sending hw/rtc code because it was suggested that the Goldfish
> implementation gets handled via the RISC-V tree as our virt board is the only
> user. I'm happy to do things differently in the future (maybe send
> goldfish-specific PRs?) if that's better for you. Just LMK what makes sense,
> I
> anticipate that this'll be a pretty low traffic device so I'm fine with pretty
> much anything.
>
Regards,
Bin
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2, Palmer Dabbelt, 2020/02/12
- [PULL 2/5] riscv: Separate FPU register size from core register size in gdbstub [v2], Palmer Dabbelt, 2020/02/12
- [PULL 1/5] riscv/virt: Add syscon reboot and poweroff DT nodes, Palmer Dabbelt, 2020/02/12
- [PULL 4/5] riscv: virt: Use Goldfish RTC device, Palmer Dabbelt, 2020/02/12
- [PULL 3/5] hw: rtc: Add Goldfish RTC device, Palmer Dabbelt, 2020/02/12
- [PULL 5/5] MAINTAINERS: Add maintainer entry for Goldfish RTC, Palmer Dabbelt, 2020/02/12
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2,
Bin Meng <=
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2, Peter Maydell, 2020/02/16