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[PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_
From: |
Peter Maydell |
Subject: |
[PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask |
Date: |
Thu, 13 Feb 2020 14:41:15 +0000 |
From: Richard Henderson <address@hidden>
CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED.
The function also takes into account bits that the cpu
does not support.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 2 --
target/arm/op_helper.c | 5 ++++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 08b2f5d73e4..694b0742983 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1209,8 +1209,6 @@ void pmu_init(ARMCPU *cpu);
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits. MRS read as zero, MSR writes ignored. */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
-/* Mask of bits which may be set by exception return copying them from SPSR */
-#define CPSR_ERET_MASK (~CPSR_RESERVED)
/* Bit definitions for M profile XPSR. Most are the same as CPSR. */
#define XPSR_EXCP 0x1ffU
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 27d16ad9ad9..acf1815ea3e 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -400,11 +400,14 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val,
uint32_t mask)
/* Write the CPSR for a 32-bit exception return */
void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
{
+ uint32_t mask;
+
qemu_mutex_lock_iothread();
arm_call_pre_el_change_hook(env_archcpu(env));
qemu_mutex_unlock_iothread();
- cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
+ mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
+ cpsr_write(env, val, mask, CPSRWriteExceptionReturn);
/* Generated code has already stored the new PC value, but
* without masking out its low bits, because which bits need
--
2.20.1
- [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID, (continued)
- [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID, Peter Maydell, 2020/02/13
- [PULL 07/46] arm/acpi: fix duplicated _UID of PCI interrupt link devices, Peter Maydell, 2020/02/13
- [PULL 08/46] arm/acpi: simplify the description of PCI _CRS, Peter Maydell, 2020/02/13
- [PULL 09/46] virt/acpi: update golden masters for DSDT update, Peter Maydell, 2020/02/13
- [PULL 12/46] target/arm: Add isar_feature tests for PAN + ATS1E1, Peter Maydell, 2020/02/13
- [PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2, Peter Maydell, 2020/02/13
- [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled, Peter Maydell, 2020/02/13
- [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Peter Maydell, 2020/02/13
- [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask, Peter Maydell, 2020/02/13
- [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask,
Peter Maydell <=
- [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot, Peter Maydell, 2020/02/13
- [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return, Peter Maydell, 2020/02/13
- [PULL 18/46] target/arm: Remove CPSR_RESERVED, Peter Maydell, 2020/02/13
- [PULL 21/46] target/arm: Update arm_mmu_idx_el for PAN, Peter Maydell, 2020/02/13
- [PULL 20/46] target/arm: Update MSR access for PAN, Peter Maydell, 2020/02/13
- [PULL 13/46] target/arm: Move LOR regdefs to file scope, Peter Maydell, 2020/02/13
- [PULL 23/46] target/arm: Set PAN bit as required on exception entry, Peter Maydell, 2020/02/13
- [PULL 27/46] target/arm: Update MSR access to UAO, Peter Maydell, 2020/02/13
- [PULL 26/46] target/arm: Add ID_AA64MMFR2_EL1, Peter Maydell, 2020/02/13
- [PULL 24/46] target/arm: Implement ATS1E1 system registers, Peter Maydell, 2020/02/13