[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 0/3] RISC-V Spike machine improvements
From: |
Anup Patel |
Subject: |
[PATCH 0/3] RISC-V Spike machine improvements |
Date: |
Fri, 14 Feb 2020 12:51:24 +0530 |
This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs
Anup Patel (3):
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
hw/riscv/spike: Allow loading firmware separately using -bios option
hw/riscv/spike: Allow more than one CPUs
hw/riscv/boot.c | 13 ++++++++-----
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 ++++--
5 files changed, 38 insertions(+), 11 deletions(-)
--
2.17.1
- [PATCH 0/3] RISC-V Spike machine improvements,
Anup Patel <=