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[PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TB
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From: |
Richard Henderson |
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Subject: |
[PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX |
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Date: |
Fri, 14 Feb 2020 11:46:41 -0800 |
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 620a429067..096a854aed 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6964,6 +6964,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_resh);
+ clear_vec_high(s, true, rd);
}
/* ZIP/UZP/TRN
--
2.20.1