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[PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON f
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From: |
Peter Maydell |
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Subject: |
[PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field |
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Date: |
Fri, 21 Feb 2020 13:07:08 +0000 |
We already define FIELD macros for ID_DFR0, so use them in the
one place where we're doing direct bit value manipulation.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 12bf9688007..1024f506c51 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
#endif
} else {
cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER,
0);
- cpu->id_dfr0 &= ~(0xf << 24);
+ cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
--
2.20.1
- [PULL 10/52] target/arm: Use bit 55 explicitly for pauth, (continued)
- [PULL 10/52] target/arm: Use bit 55 explicitly for pauth, Peter Maydell, 2020/02/21
- [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both, Peter Maydell, 2020/02/21
- [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN, Peter Maydell, 2020/02/21
- [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS, Peter Maydell, 2020/02/21
- [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae, Peter Maydell, 2020/02/21
- [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/21
- [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid, Peter Maydell, 2020/02/21
- [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/21
- [PULL 17/52] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/21
- [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/21
- [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field,
Peter Maydell <=
- [PULL 18/52] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/21
- [PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/21
- [PULL 22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/21
- [PULL 19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/21
- [PULL 23/52] target/arm: Stop assuming DBGDIDR always exists, Peter Maydell, 2020/02/21
- [PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/21
- [PULL 26/52] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/21
- [PULL 25/52] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/21
- [PULL 27/52] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/21
- [PULL 29/52] target/arm: Correct definition of PMCRDP, Peter Maydell, 2020/02/21