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[RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for deco
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree |
Date: |
Fri, 28 Feb 2020 10:43:24 -0600 |
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Tested-by: Philippe Mathieu-Daudé <address@hidden
Signed-off-by: Taylor Simpson <address@hidden>
---
target/hexagon/gen_dectree_import.c | 205 ++++++++++++++++++++++++++++++++++++
1 file changed, 205 insertions(+)
create mode 100644 target/hexagon/gen_dectree_import.c
diff --git a/target/hexagon/gen_dectree_import.c
b/target/hexagon/gen_dectree_import.c
new file mode 100644
index 0000000..4dfd4d4
--- /dev/null
+++ b/target/hexagon/gen_dectree_import.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This program generates the encodings file that is processed by
+ * the dectree.py script to produce the decoding tree. We use the C
+ * preprocessor to manipulate the files imported from the Hexagon
+ * architecture library.
+ */
+#include <stdio.h>
+#include <string.h>
+#include "opcodes.h"
+
+#define STRINGIZE(X) #X
+
+const char *opcode_names[] = {
+#define OPCODE(IID) STRINGIZE(IID)
+#include "opcodes_def_generated.h"
+ NULL
+#undef OPCODE
+};
+
+char *opcode_syntax[XX_LAST_OPCODE];
+
+/*
+ * Process the instruction definitions
+ * Scalar core instructions have the following form
+ * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
+ * "Add 32-bit registers",
+ * { RdV=RsV+RtV;})
+ * HVX instructions have the following form
+ * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)",
+ * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE,A_NOTE_MPY_RESOURCE),
+ * "Insert Word Scalar into Vector",
+ * VxV.uw[0] = RtV;)
+ */
+void opcode_init()
+{
+#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
+ opcode_syntax[TAG] = BEH;
+#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
+ opcode_syntax[TAG] = BEH;
+#include "imported/allidefs.def"
+#undef Q6INSN
+#undef EXTINSN
+}
+
+const char *opcode_rregs[] = {
+#define REGINFO(TAG, REGINFO, RREGS, WREGS) RREGS,
+#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */
+#include "op_regs_generated.h"
+ NULL
+#undef REGINFO
+#undef IMMINFO
+};
+
+const char *opcode_wregs[] = {
+#define REGINFO(TAG, REGINFO, RREGS, WREGS) WREGS,
+#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */
+#include "op_regs_generated.h"
+ NULL
+#undef REGINFO
+#undef IMMINFO
+};
+
+opcode_encoding_t opcode_encodings[] = {
+#define DEF_ENC32(TAG, ENCSTR) \
+ [TAG] = { .encoding = ENCSTR },
+#define DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) \
+ [TAG] = { .encoding = ENCSTR, .enc_class = CLASS },
+#define DEF_EXT_ENC(TAG, CLASS, ENCSTR) \
+ [TAG] = { .encoding = ENCSTR, .enc_class = CLASS },
+#include "imported/encode.def"
+#undef DEF_ENC32
+#undef DEF_ENC_SUBINSN
+#undef DEF_EXT_ENC
+};
+
+static const char * const opcode_enc_class_names[XX_LAST_ENC_CLASS] = {
+ "NORMAL",
+ "16BIT",
+ "SUBINSN_A",
+ "SUBINSN_L1",
+ "SUBINSN_L2",
+ "SUBINSN_S1",
+ "SUBINSN_S2",
+ "EXT_noext",
+ "EXT_mmvec",
+};
+
+static const char *get_opcode_enc(int opcode)
+{
+ const char *tmp = opcode_encodings[opcode].encoding;
+ if (tmp == NULL) {
+ tmp = "MISSING ENCODING";
+ }
+ return tmp;
+}
+
+static const char *get_opcode_enc_class(int opcode)
+{
+ const char *tmp = opcode_encodings[opcode].encoding;
+ if (tmp == NULL) {
+ char *test = "V6_"; /* HVX */
+ char *name = (char *)opcode_names[opcode];
+ if (strncmp(name, test, strlen(test)) == 0) {
+ return "EXT_mmvec";
+ }
+ }
+ return opcode_enc_class_names[opcode_encodings[opcode].enc_class];
+}
+
+static void gen_iset_table(FILE *out)
+{
+ int i;
+
+ fprintf(out, "iset = {\n");
+ for (i = 0; i < XX_LAST_OPCODE; i++) {
+ fprintf(out, "\t\'%s\' : {\n", opcode_names[i]);
+ fprintf(out, "\t\t\'tag\' : \'%s\',\n", opcode_names[i]);
+ fprintf(out, "\t\t\'syntax\' : \'%s\',\n", opcode_syntax[i]);
+ fprintf(out, "\t\t\'rregs\' : \'%s\',\n", opcode_rregs[i]);
+ fprintf(out, "\t\t\'wregs\' : \'%s\',\n", opcode_wregs[i]);
+ fprintf(out, "\t\t\'enc\' : \'%s\',\n", get_opcode_enc(i));
+ fprintf(out, "\t\t\'enc_class\' : \'%s\',\n", get_opcode_enc_class(i));
+ fprintf(out, "\t},\n");
+ }
+ fprintf(out, "};\n\n");
+}
+
+static void gen_tags_list(FILE *out)
+{
+ int i;
+
+ fprintf(out, "tags = [\n");
+ for (i = 0; i < XX_LAST_OPCODE; i++) {
+ fprintf(out, "\t\'%s\',\n", opcode_names[i]);
+ }
+ fprintf(out, "];\n\n");
+}
+
+static void gen_enc_ext_spaces_table(FILE *out)
+{
+ fprintf(out, "enc_ext_spaces = {\n");
+#define DEF_EXT_SPACE(SPACEID, ENCSTR) \
+ fprintf(out, "\t\'%s\' : \'%s\',\n", #SPACEID, ENCSTR);
+#include "imported/encode.def"
+#undef DEF_EXT_SPACE
+ fprintf(out, "};\n\n");
+}
+
+static void gen_subinsn_groupings_table(FILE *out)
+{
+ fprintf(out, "subinsn_groupings = {\n");
+#define DEF_PACKED32(TAG, TYPEA, TYPEB, ENCSTR) \
+ do { \
+ fprintf(out, "\t\'%s\' : {\n", #TAG); \
+ fprintf(out, "\t\t\'name\' : \'%s\',\n", #TAG); \
+ fprintf(out, "\t\t\'class_a\' : \'%s\',\n", #TYPEA); \
+ fprintf(out, "\t\t\'class_b\' : \'%s\',\n", #TYPEB); \
+ fprintf(out, "\t\t\'enc\' : \'%s\',\n", ENCSTR); \
+ fprintf(out, "\t},\n"); \
+ } while (0);
+#include "imported/encode.def"
+#undef DEF_PACKED32
+ fprintf(out, "};\n\n");
+}
+
+int main(int argc, char *argv[])
+{
+ FILE *outfile;
+
+ if (argc != 2) {
+ fprintf(stderr, "Usage: gen_dectree_import ouptputfile\n");
+ return -1;
+ }
+ outfile = fopen(argv[1], "w");
+ if (outfile == NULL) {
+ fprintf(stderr, "Cannot open %s for writing\n", argv[1]);
+ return -1;
+ }
+
+ opcode_init();
+ gen_iset_table(outfile);
+ gen_tags_list(outfile);
+ gen_enc_ext_spaces_table(outfile);
+ gen_subinsn_groupings_table(outfile);
+
+ fclose(outfile);
+ return 0;
+}
--
2.7.4
- [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h, (continued)
- [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 44/67] Hexagon TCG generation - step 06, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 31/67] Hexagon macros to interface with the generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 14/67] Hexagon instruction/packet decode, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 33/67] Hexagon instruction classes, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 41/67] Hexagon TCG generation - step 03, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 59/67] Hexagon HVX semantics generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree,
Taylor Simpson <=
- [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 06/67] Hexagon Disassembler, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 47/67] Hexagon TCG generation - step 09, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 48/67] Hexagon TCG generation - step 10, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 58/67] Hexagon HVX import macro definitions, Taylor Simpson, 2020/02/28