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[PATCH v5 01/12] target/arm: Improve masking of HCR/HCR2 RES0 bits
From: |
Richard Henderson |
Subject: |
[PATCH v5 01/12] target/arm: Improve masking of HCR/HCR2 RES0 bits |
Date: |
Fri, 28 Feb 2020 17:28:00 -0800 |
Don't merely start with v8.0, handle v7VE as well. Ensure that writes
from aarch32 mode do not change bits in the other half of the register.
Protect reads of aa64 id registers with ARM_FEATURE_AARCH64.
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 38 +++++++++++++++++++++++++-------------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6be9ffa09e..e68e16b85b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5086,11 +5086,15 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
REGINFO_SENTINEL
};
-static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
{
ARMCPU *cpu = env_archcpu(env);
- /* Begin with bits defined in base ARMv8.0. */
- uint64_t valid_mask = MAKE_64BIT_MASK(0, 34);
+
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
+ } else {
+ valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
+ }
if (arm_feature(env, ARM_FEATURE_EL3)) {
valid_mask &= ~HCR_HCD;
@@ -5104,14 +5108,17 @@ static void hcr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
*/
valid_mask &= ~HCR_TSC;
}
- if (cpu_isar_feature(aa64_vh, cpu)) {
- valid_mask |= HCR_E2H;
- }
- if (cpu_isar_feature(aa64_lor, cpu)) {
- valid_mask |= HCR_TLOR;
- }
- if (cpu_isar_feature(aa64_pauth, cpu)) {
- valid_mask |= HCR_API | HCR_APK;
+
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
+ if (cpu_isar_feature(aa64_vh, cpu)) {
+ valid_mask |= HCR_E2H;
+ }
+ if (cpu_isar_feature(aa64_lor, cpu)) {
+ valid_mask |= HCR_TLOR;
+ }
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
+ valid_mask |= HCR_API | HCR_APK;
+ }
}
/* Clear RES0 bits. */
@@ -5143,12 +5150,17 @@ static void hcr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
arm_cpu_update_vfiq(cpu);
}
+static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ do_hcr_write(env, value, 0);
+}
+
static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
value = deposit64(env->cp15.hcr_el2, 32, 32, value);
- hcr_write(env, NULL, value);
+ do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32));
}
static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -5156,7 +5168,7 @@ static void hcr_writelow(CPUARMState *env, const
ARMCPRegInfo *ri,
{
/* Handle HCR write, i.e. write to low half of HCR_EL2 */
value = deposit64(env->cp15.hcr_el2, 0, 32, value);
- hcr_write(env, NULL, value);
+ do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32));
}
/*
--
2.20.1
- [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps, Richard Henderson, 2020/02/28
- [PATCH v5 01/12] target/arm: Improve masking of HCR/HCR2 RES0 bits,
Richard Henderson <=
- [PATCH v5 02/12] target/arm: Add HCR_EL2 bit definitions from ARMv8.6, Richard Henderson, 2020/02/28
- [PATCH v5 05/12] target/arm: Improve masking in arm_hcr_el2_eff, Richard Henderson, 2020/02/28
- [PATCH v5 04/12] target/arm: Remove EL2 and EL3 setup from user-only, Richard Henderson, 2020/02/28
- [PATCH v5 06/12] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/28
- [PATCH v5 08/12] target/arm: Honor the HCR_EL2.TACR bit, Richard Henderson, 2020/02/28
- [PATCH v5 11/12] target/arm: Honor the HCR_EL2.TTLB bit, Richard Henderson, 2020/02/28
- [PATCH v5 07/12] target/arm: Honor the HCR_EL2.TSW bit, Richard Henderson, 2020/02/28
- [PATCH v5 09/12] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/28
- [PATCH v5 10/12] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/28
- [PATCH v5 12/12] tests/tcg/aarch64: Add newline in pauth-1 printf, Richard Henderson, 2020/02/28