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[PULL 02/38] target/riscv: Add the Hypervisor extension
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From: |
Palmer Dabbelt |
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Subject: |
[PULL 02/38] target/riscv: Add the Hypervisor extension |
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Date: |
Mon, 2 Mar 2020 16:48:12 -0800 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
+#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
--
2.25.0.265.gbab2e86ba0-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3, Palmer Dabbelt, 2020/03/02
- [PULL 04/38] target/riscv: Add support for the new execption numbers, Palmer Dabbelt, 2020/03/02
- [PULL 05/38] target/riscv: Rename the H irqs to VS irqs, Palmer Dabbelt, 2020/03/02
- [PULL 14/38] target/riscv: Add virtual register swapping function, Palmer Dabbelt, 2020/03/02
- [PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension, Palmer Dabbelt, 2020/03/02
- [PULL 02/38] target/riscv: Add the Hypervisor extension,
Palmer Dabbelt <=
- [PULL 03/38] target/riscv: Add the Hypervisor CSRs to CPUState, Palmer Dabbelt, 2020/03/02
- [PULL 07/38] target/riscv: Add the force HS exception mode, Palmer Dabbelt, 2020/03/02
- [PULL 09/38] target/riscv: Print priv and virt in disas log, Palmer Dabbelt, 2020/03/02
- [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, Palmer Dabbelt, 2020/03/02
- [PULL 21/38] target/riscv: Add hypvervisor trap support, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 06/38] target/riscv: Add the virtulisation mode, Palmer Dabbelt, 2020/03/02