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[PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation
From: |
Palmer Dabbelt |
Subject: |
[PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation |
Date: |
Mon, 2 Mar 2020 16:48:27 -0800 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 918678789a..2e6700bbeb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -743,8 +743,19 @@ static int write_sbadaddr(CPURISCVState *env, int csrno,
target_ulong val)
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ int ret;
+
+ if (riscv_cpu_virt_enabled(env)) {
+ /* Shift the new values to line up with the VS bits */
+ ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
+ (write_mask & sip_writable_mask) << 1 & env->mideleg);
+ ret &= vsip_writable_mask;
+ ret >>= 1;
+ } else {
+ ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
write_mask & env->mideleg & sip_writable_mask);
+ }
+
*ret_value &= env->mideleg;
return ret;
}
--
2.25.0.265.gbab2e86ba0-goog
- [PULL 09/38] target/riscv: Print priv and virt in disas log, (continued)
- [PULL 09/38] target/riscv: Print priv and virt in disas log, Palmer Dabbelt, 2020/03/02
- [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, Palmer Dabbelt, 2020/03/02
- [PULL 21/38] target/riscv: Add hypvervisor trap support, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 06/38] target/riscv: Add the virtulisation mode, Palmer Dabbelt, 2020/03/02
- [PULL 08/38] target/riscv: Fix CSR perm checking for HS mode, Palmer Dabbelt, 2020/03/02
- [PULL 11/38] target/riscv: Add Hypervisor CSR access functions, Palmer Dabbelt, 2020/03/02
- [PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation,
Palmer Dabbelt <=
- [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes, Palmer Dabbelt, 2020/03/02
- [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1, Palmer Dabbelt, 2020/03/02
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage, Palmer Dabbelt, 2020/03/02
- [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops, Palmer Dabbelt, 2020/03/02
- [PULL 30/38] target/riscv: Implement second stage MMU, Palmer Dabbelt, 2020/03/02
- [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails, Palmer Dabbelt, 2020/03/02
- [PULL 01/38] target/riscv: Convert MIP CSR to target_ulong, Palmer Dabbelt, 2020/03/02
- [PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 23/38] target/riscv: Add hfence instructions, Palmer Dabbelt, 2020/03/02