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Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3
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From: |
Peter Maydell |
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Subject: |
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3 |
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Date: |
Tue, 3 Mar 2020 12:03:46 +0000 |
On Tue, 3 Mar 2020 at 00:48, Palmer Dabbelt <address@hidden> wrote:
>
> The following changes since commit 8b6b68e05b43f976714ca1d2afe01a64e1d82cba:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2020-02-27 19:15:15 +0000)
>
> are available in the Git repository at:
>
> address@hidden:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf3
>
> for you to fetch changes up to 5f3616ccceb5d5c49f99838c78498e581fb42fc5:
>
> hw/riscv: Provide rdtime callback for TCG in CLINT emulation (2020-02-27
> 13:46:37 -0800)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 3
>
> This pull request is almost entirely an implementation of the draft hypervisor
> extension. This extension is still in draft and is expected to have
> incompatible changes before being frozen, but we've had good luck managing
> other RISC-V draft extensions in QEMU so far.
>
> Additionally, there's a fix to PCI addressing and some improvements to the
> M-mode timer.
>
> This boots linux and passes make check for me.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, (continued)
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, Palmer Dabbelt, 2020/03/02
- [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Palmer Dabbelt, 2020/03/02
- [PULL 36/38] riscv: virt: Allow PCI address 0, Palmer Dabbelt, 2020/03/02
- [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension, Palmer Dabbelt, 2020/03/02
- [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode, Palmer Dabbelt, 2020/03/02
- [PULL 26/38] target/riscv: Disable guest FP support based on virtual status, Palmer Dabbelt, 2020/03/02
- [PULL 32/38] target/riscv: Set htval and mtval2 on execptions, Palmer Dabbelt, 2020/03/02
- [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation, Palmer Dabbelt, 2020/03/02
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3,
Peter Maydell <=