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Re: [PATCH v1 5/5] tests/acceptance: disable two more tests while in CI
From: |
Alex Bennée |
Subject: |
Re: [PATCH v1 5/5] tests/acceptance: disable two more tests while in CI |
Date: |
Tue, 10 Mar 2020 07:34:24 +0000 |
User-agent: |
mu4e 1.3.9; emacs 28.0.50 |
Alex Bennée <address@hidden> writes:
> These keep timing out on Travis. The reason is unknown so add a FIXME
> for those who want to track down exactly why this is happening. In the
> meantime you can still run check-acceptance manually without change.
>
> Signed-off-by: Alex Bennée <address@hidden>
> ---
> tests/acceptance/machine_mips_malta.py | 2 ++
> tests/acceptance/machine_sparc_leon3.py | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/tests/acceptance/machine_mips_malta.py
> b/tests/acceptance/machine_mips_malta.py
> index 92b4f28a112..deebf532e95 100644
> --- a/tests/acceptance/machine_mips_malta.py
> +++ b/tests/acceptance/machine_mips_malta.py
> @@ -99,6 +99,8 @@ class MaltaMachineFramebuffer(Test):
> """
> self.do_test_i6400_framebuffer_logo(1)
>
> + # FIXME: why does this keep timing out on Travis?
> + @skipIf(os.getenv('CONTINUOUS_INTEGRATION'), 'Running on Travis-CI')
> def test_mips_malta_i6400_framebuffer_logo_7cores(self):
> """
> :avocado: tags=arch:mips64el
<snip>
I can replicate this on my local machine with either 7 or 8 core runs by
using tasksel to limit the threads to two cores (like the Travis VM). I
suspect this is a MTTCG bug because it smell racy.
The failure I see is:
Brought up 8 CPUs
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns:
19112604462750000 ns
NET: Registered protocol family 16
pm-cps: CPC does not support clock gating
vgaarb: loaded
SCSI subsystem initialized
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff]
pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size)
pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size)
pci 0000:00:0a.1: legacy IDE quirk: reg 0x10: [io 0x01f0-0x01f7]
pci 0000:00:0a.1: legacy IDE quirk: reg 0x14: [io 0x03f6]
pci 0000:00:0a.1: legacy IDE quirk: reg 0x18: [io 0x0170-0x0177]
pci 0000:00:0a.1: legacy IDE quirk: reg 0x1c: [io 0x0376]
At which point the kernel doesn't complete and ends up not progressing
beyond this point. Possibly an IRQ gets missed?
Ideas?
--
Alex Bennée
- [PATCH v1 0/5] testing updates (docker and acceptance CI tweaks), Alex Bennée, 2020/03/09
- [PATCH v1 1/5] tests/docker: Install tools to cross-debug and build Linux kernels, Alex Bennée, 2020/03/09
- [PATCH v1 2/5] tests/docker: Update VirGL git repository URL, Alex Bennée, 2020/03/09
- [PATCH v1 5/5] tests/acceptance: disable two more tests while in CI, Alex Bennée, 2020/03/09
- Re: [PATCH v1 5/5] tests/acceptance: disable two more tests while in CI,
Alex Bennée <=
- [PATCH v1 3/5] tests/docker: Remove obsolete VirGL --with-glx configure option, Alex Bennée, 2020/03/09
- [PATCH v1 4/5] tests/docker: Update VirGL to v0.8.0, Alex Bennée, 2020/03/09
- Re: [PATCH v1 0/5] testing updates (docker and acceptance CI tweaks), no-reply, 2020/03/09