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[PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user
From: |
Richard Henderson |
Subject: |
[PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only |
Date: |
Thu, 12 Mar 2020 12:41:50 -0700 |
We need this to raise unaligned exceptions from user mode.
Signed-off-by: Richard Henderson <address@hidden>
---
v6: Use EXCP_UNALIGNED for user-only and update cpu_loop.c.
---
linux-user/aarch64/cpu_loop.c | 7 ++++++
linux-user/arm/cpu_loop.c | 7 ++++++
target/arm/cpu.c | 2 +-
target/arm/tlb_helper.c | 41 ++++++++++++++++++++++-------------
4 files changed, 41 insertions(+), 16 deletions(-)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index bbe9fefca8..3cca637bb9 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -121,6 +121,13 @@ void cpu_loop(CPUARMState *env)
info._sifields._sigfault._addr = env->exception.vaddress;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case EXCP_UNALIGNED:
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = TARGET_BUS_ADRALN;
+ info._sifields._sigfault._addr = env->exception.vaddress;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_DEBUG:
case EXCP_BKPT:
info.si_signo = TARGET_SIGTRAP;
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index cf618daa1c..d2ce78ae73 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -395,6 +395,13 @@ void cpu_loop(CPUARMState *env)
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
}
break;
+ case EXCP_UNALIGNED:
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = TARGET_BUS_ADRALN;
+ info._sifields._sigfault._addr = env->exception.vaddress;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_DEBUG:
excp_debug:
info.si_signo = TARGET_SIGTRAP;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3623ecefbd..cb3c3fe8c2 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2831,8 +2831,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
-#if !defined(CONFIG_USER_ONLY)
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
+#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index e63f8bda29..44d7bcc783 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -107,21 +107,6 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu,
vaddr addr,
raise_exception(env, exc, syn, target_el);
}
-/* Raise a data fault alignment exception for the specified virtual address */
-void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- ARMMMUFaultInfo fi = {};
-
- /* now we have a real cpu fault */
- cpu_restore_state(cs, retaddr, true);
-
- fi.type = ARMFault_Alignment;
- arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
-}
-
/*
* arm_cpu_do_transaction_failed: handle a memory system error response
* (eg "no device/memory present at address") by raising an external abort
@@ -198,3 +183,29 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
}
#endif
}
+
+/* Raise a data fault alignment exception for the specified virtual address */
+void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+
+#ifdef CONFIG_USER_ONLY
+ cpu->env.exception.vaddress = vaddr;
+ /*
+ * For HW, this is EXCP_DATA_ABORT with a proper syndrome.
+ * Make it easier for ourselves in linux-user/arm/cpu_loop.c.
+ */
+ cs->exception_index = EXCP_UNALIGNED;
+ cpu_loop_exit_restore(cs, retaddr);
+#else
+ ARMMMUFaultInfo fi = {};
+
+ /* now we have a real cpu fault */
+ cpu_restore_state(cs, retaddr, true);
+
+ fi.type = ARMFault_Alignment;
+ arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
+#endif
+}
--
2.20.1
- [PATCH v6 04/42] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, (continued)
- [PATCH v6 04/42] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Richard Henderson, 2020/03/12
- [PATCH v6 05/42] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Richard Henderson, 2020/03/12
- [PATCH v6 06/42] target/arm: Add DISAS_UPDATE_NOCHAIN, Richard Henderson, 2020/03/12
- [PATCH v6 07/42] target/arm: Add MTE system registers, Richard Henderson, 2020/03/12
- [PATCH v6 08/42] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/03/12
- [PATCH v6 11/42] target/arm: Implement the GMI instruction, Richard Henderson, 2020/03/12
- [PATCH v6 10/42] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/03/12
- [PATCH v6 09/42] target/arm: Implement the IRG instruction, Richard Henderson, 2020/03/12
- [PATCH v6 14/42] target/arm: Add helper_probe_access, Richard Henderson, 2020/03/12
- [PATCH v6 12/42] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/03/12
- [PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only,
Richard Henderson <=
- [PATCH v6 15/42] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/03/12
- [PATCH v6 16/42] target/arm: Implement the STGP instruction, Richard Henderson, 2020/03/12
- [PATCH v6 17/42] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/03/12
- [PATCH v6 22/42] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/03/12
- [PATCH v6 21/42] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/03/12
- [PATCH v6 20/42] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/03/12
- [PATCH v6 23/42] target/arm: Add gen_mte_check1, Richard Henderson, 2020/03/12
- [PATCH v6 24/42] target/arm: Add gen_mte_checkN, Richard Henderson, 2020/03/12
- [PATCH v6 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/03/12
- [PATCH v6 18/42] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/03/12