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Re: [PATCH v5 05/60] target/riscv: add vector stride load and store inst

From: LIU Zhiwei
Subject: Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
Date: Sat, 14 Mar 2020 09:49:34 +0800
User-agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0

On 2020/3/14 9:26, Richard Henderson wrote:
On 3/13/20 2:32 PM, LIU Zhiwei wrote:
+/* check functions */
+static bool vext_check_isa_ill(DisasContext *s, target_ulong isa)
+    return !s->vill && ((s->misa & isa) == isa);
I don't think we need a new function to check ISA.
I don't think so.

Although there is a riscv_has_ext(env, isa) in cpu.h, it is not proper in this
as it is in translation time and  usually DisasContext   is used here instead
In translate.c we have has_ext() for this purpose.
Yes, I will use it.
I think you don't need to test has_ext(s, RVV) at all,
because in cpu_get_tb_cpu_state(), you already tested
RVV, and set VILL if RVV was not present.

Thus testing vill here is sufficient.  A comment here
to remind us of that fact would be appropriate.
Yes, I forgot it. I will keep the function and add a comment.
For those few cases where you have an extension beyond
RVV, e.g. amo_check() I think you should simply use
has_ext() like so:

static bool amo_check(DisasContext *s, arg_rwdvm *a)
     return (!s->vill &&
             has_ext(s, RVA) &&
Yes, I will fix it in that patch.


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