Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply

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Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply

From:	LIU Zhiwei
Subject:	Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions
Date:	Sat, 14 Mar 2020 15:02:45 +0800
User-agent:	Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0



On 2020/3/14 14:52, Richard Henderson wrote:

On 3/12/20 7:58 AM, LIU Zhiwei wrote:

+static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
+{
+    uint64_t hi_64, lo_64, abs_s2 = s2;
+
+    if (s2 < 0) {
+        abs_s2 = -s2;
+    }
+    mulu64(&lo_64, &hi_64, abs_s2, s1);
+    if ((int64_t)(s2 ^ s1) < 0) {

Why would the sign of s1 be relevant?
It's always unsigned.

Yes, it is a bug. Thanks for pointing that.

Zhiwei

We have code for this in e.g. tcg_gen_mulsu2_i64

     mulu4(&lo, &hi, s1, s2);
     if ((int64_t)s2 < 0) {
         hi -= s2;
     }


r~

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[PATCH v5 13/60] target/riscv: vector single-width bit shift instructions, (continued)
- [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions, Richard Henderson, 2020/03/14
- [PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions, Richard Henderson, 2020/03/14
- [PATCH v5 15/60] target/riscv: vector integer comparison instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 15/60] target/riscv: vector integer comparison instructions, Richard Henderson, 2020/03/14
- [PATCH v5 16/60] target/riscv: vector integer min/max instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 16/60] target/riscv: vector integer min/max instructions, Richard Henderson, 2020/03/14
- [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions, Richard Henderson, 2020/03/14
    - Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei <=
- [PATCH v5 18/60] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 18/60] target/riscv: vector integer divide instructions, Richard Henderson, 2020/03/14
- [PATCH v5 19/60] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 19/60] target/riscv: vector widening integer multiply instructions, Richard Henderson, 2020/03/14
- [PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions, Richard Henderson, 2020/03/14
- [PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions, Richard Henderson, 2020/03/14
- [PATCH v5 22/60] target/riscv: vector integer merge and move instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions, Richard Henderson, 2020/03/14

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