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[PULL 08/61] WHPX: Use QEMU values for trapped CPUID
From: |
Paolo Bonzini |
Subject: |
[PULL 08/61] WHPX: Use QEMU values for trapped CPUID |
Date: |
Mon, 16 Mar 2020 22:26:35 +0100 |
From: Sunil Muthuswamy <address@hidden>
Currently, WHPX is using some default values for the trapped CPUID
functions. These were not in sync with the QEMU values because the
CPUID values were never set with WHPX during VCPU initialization.
Additionally, at the moment, WHPX doesn't support setting CPUID
values in the hypervisor at runtime (i.e. after the partition has
been setup). That is needed to be able to set the CPUID values in
the hypervisor during VCPU init.
Until that support comes, use the QEMU values for the trapped CPUIDs.
Signed-off-by: Sunil Muthuswamy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
target/i386/whpx-all.c | 42 ++++++++++++++++++------------------------
1 file changed, 18 insertions(+), 24 deletions(-)
diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c
index b947eb1..cb863b7 100644
--- a/target/i386/whpx-all.c
+++ b/target/i386/whpx-all.c
@@ -1044,38 +1044,32 @@ static int whpx_vcpu_run(CPUState *cpu)
WHV_REGISTER_VALUE reg_values[5];
WHV_REGISTER_NAME reg_names[5];
UINT32 reg_count = 5;
- UINT64 rip, rax, rcx, rdx, rbx;
+ UINT64 cpuid_fn, rip = 0, rax = 0, rcx = 0, rdx = 0, rbx = 0;
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
memset(reg_values, 0, sizeof(reg_values));
rip = vcpu->exit_ctx.VpContext.Rip +
vcpu->exit_ctx.VpContext.InstructionLength;
- switch (vcpu->exit_ctx.CpuidAccess.Rax) {
- case 1:
- rax = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
- /* Advertise that we are running on a hypervisor */
- rcx =
- vcpu->exit_ctx.CpuidAccess.DefaultResultRcx |
- CPUID_EXT_HYPERVISOR;
-
- rdx = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
- rbx = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
- break;
+ cpuid_fn = vcpu->exit_ctx.CpuidAccess.Rax;
+
+ /*
+ * Ideally, these should be supplied to the hypervisor during VCPU
+ * initialization and it should be able to satisfy this request.
+ * But, currently, WHPX doesn't support setting CPUID values in the
+ * hypervisor once the partition has been setup, which is too late
+ * since VCPUs are realized later. For now, use the values from
+ * QEMU to satisfy these requests, until WHPX adds support for
+ * being able to set these values in the hypervisor at runtime.
+ */
+ cpu_x86_cpuid(env, cpuid_fn, 0, (UINT32 *)&rax, (UINT32 *)&rbx,
+ (UINT32 *)&rcx, (UINT32 *)&rdx);
+ switch (cpuid_fn) {
case 0x80000001:
- rax = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
/* Remove any support of OSVW */
- rcx =
- vcpu->exit_ctx.CpuidAccess.DefaultResultRcx &
- ~CPUID_EXT3_OSVW;
-
- rdx = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
- rbx = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
+ rcx &= ~CPUID_EXT3_OSVW;
break;
- default:
- rax = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
- rcx = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;
- rdx = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
- rbx = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
}
reg_names[0] = WHvX64RegisterRip;
--
1.8.3.1
- [PULL 00/61] Misc patches for soft freeze, Paolo Bonzini, 2020/03/16
- [PULL 02/61] optionrom/pvh: scan entire RSDP Area, Paolo Bonzini, 2020/03/16
- [PULL 01/61] scsi/qemu-pr-helper: Fix out-of-bounds access to trnptid_list[], Paolo Bonzini, 2020/03/16
- [PULL 04/61] misc: Replace zero-length arrays with flexible array member (manual), Paolo Bonzini, 2020/03/16
- [PULL 05/61] configure: add configure option avx512f_opt, Paolo Bonzini, 2020/03/16
- [PULL 08/61] WHPX: Use QEMU values for trapped CPUID,
Paolo Bonzini <=
- [PULL 03/61] misc: Replace zero-length arrays with flexible array member (automatic), Paolo Bonzini, 2020/03/16
- [PULL 06/61] util: add util function buffer_zero_avx512(), Paolo Bonzini, 2020/03/16
- [PULL 07/61] WHPX: TSC get and set should be dependent on VM state, Paolo Bonzini, 2020/03/16
- [PULL 10/61] hw/i386/intel_iommu: Fix out-of-bounds access on guest IRT, Paolo Bonzini, 2020/03/16
- [PULL 09/61] MAINTAINERS: Add entry for Guest X86 HAXM CPUs, Paolo Bonzini, 2020/03/16