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[PULL 01/13] hw/registerfields.h: Add 8bit and 16bit register macros
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 01/13] hw/registerfields.h: Add 8bit and 16bit register macros |
Date: |
Tue, 17 Mar 2020 17:36:04 +0100 |
From: Yoshinori Sato <address@hidden>
Some RX peripheral use 8bit and 16bit registers.
Add the 8bit and 16bit APIs.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Yoshinori Sato <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
include/hw/registerfields.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..0407edb7ec 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 4 };
+#define REG8(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 2 };
+
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -34,6 +42,12 @@
MAKE_64BIT_MASK(shift, length)};
/* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field) \
+ extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field) \
+ extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
#define FIELD_EX32(storage, reg, field) \
extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +63,22 @@
* Assigning values larger then the target field will result in
* compilation warnings.
*/
+#define FIELD_DP8(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint8_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+#define FIELD_DP16(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint16_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
#define FIELD_DP32(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
--
2.21.1
- [PULL 00/13] target: Add the Renesas RX architecture, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 01/13] hw/registerfields.h: Add 8bit and 16bit register macros,
Philippe Mathieu-Daudé <=
- [PULL 02/13] MAINTAINERS: Add entry for the Renesas RX architecture, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 04/13] target/rx: TCG helpers, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 07/13] target/rx: Disassemble rx_index_addr into a string, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 09/13] target/rx: Use prt_ldmi for XCHG_mr disassembly, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 05/13] target/rx: CPU definitions, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 08/13] target/rx: Replace operand with prt_ldmi in disassembler, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 12/13] target/rx: Dump bytes for each insn during disassembly, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 10/13] target/rx: Emit all disassembly in one prt(), Philippe Mathieu-Daudé, 2020/03/17
- [PULL 11/13] target/rx: Collect all bytes during disassembly, Philippe Mathieu-Daudé, 2020/03/17
- [PULL 06/13] target/rx: RX disassembler, Philippe Mathieu-Daudé, 2020/03/17