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Re: [PATCH v6 57/61] target/riscv: floating-point scalar move instructio
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v6 57/61] target/riscv: floating-point scalar move instructions |
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Date: |
Fri, 27 Mar 2020 20:44:42 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> +/* Floating-Point Scalar Move Instructions */
> +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
> +{
> + if (!s->vill && has_ext(s, RVF) &&
> + (s->mstatus_fs != 0) && (s->sew != 0)) {
> +#ifdef HOST_WORDS_BIGENDIAN
> + int ofs = vreg_ofs(s, a->rs2) + ((7 >> s->sew) << s->sew);
> +#else
> + int ofs = vreg_ofs(s, a->rs2);
> +#endif
Use endian_ofs from patch 55.
> + switch (s->sew) {
> + case MO_8:
> + tcg_gen_ld8u_i64(cpu_fpr[a->rd], cpu_env, ofs);
> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
> + 0xffffffffffffff00ULL);
> + break;
MO_8 should be illegal.
> + case MO_16:
> + tcg_gen_ld16u_i64(cpu_fpr[a->rd], cpu_env, ofs);
> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
> + 0xffffffffffff0000ULL);
> + break;
> + case MO_32:
> + tcg_gen_ld32u_i64(cpu_fpr[a->rd], cpu_env, ofs);
> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
> + 0xffffffff00000000ULL);
> + break;
> + default:
> + if (has_ext(s, RVD)) {
> + tcg_gen_ld_i64(cpu_fpr[a->rd], cpu_env, ofs);
> + } else {
> + tcg_gen_ld32u_i64(cpu_fpr[a->rd], cpu_env, ofs);
> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
> + 0xffffffff00000000ULL);
> + }
> + break;
Maybe better with MO_64 and default: g_assert_not_reached().
> +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
> +{
> + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
> + TCGv_ptr dest;
> + TCGv_i64 src1;
> + static gen_helper_vfmv_s_f * const fns[3] = {
> + gen_helper_vfmv_s_f_h,
> + gen_helper_vfmv_s_f_w,
> + gen_helper_vfmv_s_f_d
You shouldn't need to duplicate the vmv_s_x_* helpers.
r~
- [PATCH v6 50/61] target/riscv: vector mask population count vmpopc, (continued)
- [PATCH v6 50/61] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/03/17
- [PATCH v6 51/61] target/riscv: vmfirst find-first-set mask bit, LIU Zhiwei, 2020/03/17
- [PATCH v6 52/61] target/riscv: set-X-first mask bit, LIU Zhiwei, 2020/03/17
- [PATCH v6 53/61] target/riscv: vector iota instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 54/61] target/riscv: vector element index instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 55/61] target/riscv: integer extract instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 56/61] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/03/17
- Re: [PATCH v6 57/61] target/riscv: floating-point scalar move instructions,
Richard Henderson <=
- [PATCH v6 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 60/61] target/riscv: vector compress instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/03/17