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[PATCH RFC v2 9/9] target/riscv: add host cpu type
From: |
Yifei Jiang |
Subject: |
[PATCH RFC v2 9/9] target/riscv: add host cpu type |
Date: |
Sat, 11 Apr 2020 12:14:27 +0800 |
Currently, host cpu is inherited simply.
Signed-off-by: Yifei Jiang <address@hidden>
Signed-off-by: Yipeng Yin <address@hidden>
---
target/riscv/cpu.c | 6 ++++++
target/riscv/cpu.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a6af13ab9..e5b42c3a54 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
set_feature(env, RISCV_FEATURE_PMP);
}
+static void riscv_host_cpu_init(Object *obj)
+{
+}
+
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -615,6 +619,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
/* Depreacted */
DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
@@ -623,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
/* Deprecated */
DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dcff112c5f..4901fd8061 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -39,6 +39,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
/* Deprecated */
#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
--
2.19.1
- [PATCH RFC v2 0/9] Add riscv kvm accel support, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 5/9] target/riscv: Implement kvm_arch_put_registers, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 9/9] target/riscv: add host cpu type,
Yifei Jiang <=
- [PATCH RFC v2 4/9] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 6/9] target/riscv: Support start kernel directly by KVM, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 1/9] linux-header: Update linux/kvm.h, Yifei Jiang, 2020/04/11
- [PATCH RFC v2 3/9] target/riscv: Implement function kvm_arch_init_vcpu, Yifei Jiang, 2020/04/11
- Re: [PATCH RFC v2 0/9] Add riscv kvm accel support, no-reply, 2020/04/11