[PATCH 07/15] KVM: MIPS: Introduce and use cpu_guest_has

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[PATCH 07/15] KVM: MIPS: Introduce and use cpu_guest_has_ldpte

From:	Huacai Chen
Subject:	[PATCH 07/15] KVM: MIPS: Introduce and use cpu_guest_has_ldpte
Date:	Mon, 13 Apr 2020 15:30:16 +0800

Loongson-3 has lddir/ldpte instructions and their related CP0 registers
are the same as HTW. So we introduce a cpu_guest_has_ldpte flag and use
it to indicate whether we need to save/restore HTW related CP0 registers
(PWBase, PWSize, PWField and PWCtl).

Signed-off-by: Huacai Chen <address@hidden>
Co-developed-by: Jiaxun Yang <address@hidden>
---
 arch/mips/include/asm/cpu-features.h |  3 +++
 arch/mips/kernel/cpu-probe.c         |  1 +
 arch/mips/kvm/vz.c                   | 26 +++++++++++++-------------
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index de44c92..c576aad 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -665,6 +665,9 @@
 #ifndef cpu_guest_has_htw
 #define cpu_guest_has_htw      (cpu_data[0].guest.options & MIPS_CPU_HTW)
 #endif
+#ifndef cpu_guest_has_ldpte
+#define cpu_guest_has_ldpte    (cpu_data[0].guest.options & MIPS_CPU_LDPTE)
+#endif
 #ifndef cpu_guest_has_mvh
 #define cpu_guest_has_mvh      (cpu_data[0].guest.options & MIPS_CPU_MVH)
 #endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f21a230..5bf0821 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1966,6 +1966,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips 
*c, unsigned int cpu)
                set_isa(c, MIPS_CPU_ISA_M64R2);
                decode_configs(c);
                c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+               c->guest.options |= MIPS_CPU_LDPTE;
                c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
                        MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 17932ab..422cd06 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1706,7 +1706,7 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu 
*vcpu)
                ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
        if (cpu_guest_has_segments)
                ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
-       if (cpu_guest_has_htw)
+       if (cpu_guest_has_htw || cpu_guest_has_ldpte)
                ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
        if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar)
                ret += 1 + ARRAY_SIZE(vcpu->arch.maar);
@@ -1755,7 +1755,7 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, 
u64 __user *indices)
                        return -EFAULT;
                indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
        }
-       if (cpu_guest_has_htw) {
+       if (cpu_guest_has_htw || cpu_guest_has_ldpte) {
                if (copy_to_user(indices, kvm_vz_get_one_regs_htw,
                                 sizeof(kvm_vz_get_one_regs_htw)))
                        return -EFAULT;
@@ -1878,17 +1878,17 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
                *v = read_gc0_segctl2();
                break;
        case KVM_REG_MIPS_CP0_PWBASE:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                *v = read_gc0_pwbase();
                break;
        case KVM_REG_MIPS_CP0_PWFIELD:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                *v = read_gc0_pwfield();
                break;
        case KVM_REG_MIPS_CP0_PWSIZE:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                *v = read_gc0_pwsize();
                break;
@@ -1896,7 +1896,7 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
                *v = (long)read_gc0_wired();
                break;
        case KVM_REG_MIPS_CP0_PWCTL:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                *v = read_gc0_pwctl();
                break;
@@ -2101,17 +2101,17 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
                write_gc0_segctl2(v);
                break;
        case KVM_REG_MIPS_CP0_PWBASE:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                write_gc0_pwbase(v);
                break;
        case KVM_REG_MIPS_CP0_PWFIELD:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                write_gc0_pwfield(v);
                break;
        case KVM_REG_MIPS_CP0_PWSIZE:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                write_gc0_pwsize(v);
                break;
@@ -2119,7 +2119,7 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
                change_gc0_wired(MIPSR6_WIRED_WIRED, v);
                break;
        case KVM_REG_MIPS_CP0_PWCTL:
-               if (!cpu_guest_has_htw)
+               if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
                        return -EINVAL;
                write_gc0_pwctl(v);
                break;
@@ -2580,7 +2580,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int 
cpu)
        }
 
        /* restore HTW registers */
-       if (cpu_guest_has_htw) {
+       if (cpu_guest_has_htw || cpu_guest_has_ldpte) {
                kvm_restore_gc0_pwbase(cop0);
                kvm_restore_gc0_pwfield(cop0);
                kvm_restore_gc0_pwsize(cop0);
@@ -2685,8 +2685,8 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu)
        }
 
        /* save HTW registers if enabled in guest */
-       if (cpu_guest_has_htw &&
-           kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) {
+       if (cpu_guest_has_ldpte || (cpu_guest_has_htw &&
+           kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW)) {
                kvm_save_gc0_pwbase(cop0);
                kvm_save_gc0_pwfield(cop0);
                kvm_save_gc0_pwsize(cop0);
-- 
2.7.0

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[PATCH 01/15] mips: define pud_index() regardless of page table folding, (continued)
- [PATCH 01/15] mips: define pud_index() regardless of page table folding, Huacai Chen, 2020/04/13
- [PATCH 02/15] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(&boot_cpu_data), Huacai Chen, 2020/04/13
  - Re: [PATCH 02/15] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(&boot_cpu_data), Sasha Levin, 2020/04/21
    - Re: [PATCH 02/15] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(&boot_cpu_data), chen huacai, 2020/04/22
- [PATCH 03/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits, Huacai Chen, 2020/04/13
  - Re: [PATCH 03/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits, Sasha Levin, 2020/04/21
    - Re: [PATCH 03/15] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits, chen huacai, 2020/04/22
- [PATCH 04/15] KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16, Huacai Chen, 2020/04/13
- [PATCH 05/15] KVM: MIPS: Add EVENTFD support which is needed by VHOST, Huacai Chen, 2020/04/13
- [PATCH 06/15] KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd, Huacai Chen, 2020/04/13
- [PATCH 07/15] KVM: MIPS: Introduce and use cpu_guest_has_ldpte, Huacai Chen <=
- [PATCH 08/15] KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3, Huacai Chen, 2020/04/13
- [PATCH 09/15] KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3, Huacai Chen, 2020/04/13
- [PATCH 10/15] KVM: MIPS: Add more types of virtual interrupts, Huacai Chen, 2020/04/13
- [PATCH 11/15] KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support, Huacai Chen, 2020/04/13
- [PATCH 12/15] KVM: MIPS: Add CPUCFG emulation for Loongson-3, Huacai Chen, 2020/04/13
- [PATCH 13/15] KVM: MIPS: Add CONFIG6 and DIAG registers emulation, Huacai Chen, 2020/04/13
  - Re: [PATCH 13/15] KVM: MIPS: Add CONFIG6 and DIAG registers emulation, Jiaxun Yang, 2020/04/13
    - Re: [PATCH 13/15] KVM: MIPS: Add CONFIG6 and DIAG registers emulation, Huacai Chen, 2020/04/19
- [PATCH 14/15] KVM: MIPS: Add more MMIO load/store instructions emulation, Huacai Chen, 2020/04/13
- [PATCH 15/15] KVM: MIPS: Enable KVM support for Loongson-3, Huacai Chen, 2020/04/13

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