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[PULL 3/6] riscv: AND stage-1 and stage-2 protection flags
From: |
Palmer Dabbelt |
Subject: |
[PULL 3/6] riscv: AND stage-1 and stage-2 protection flags |
Date: |
Tue, 21 Apr 2020 12:09:58 -0700 |
From: Alistair Francis <address@hidden>
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 48e112808b..700ef052b0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -705,7 +705,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
#ifndef CONFIG_USER_ONLY
vaddr im_address;
hwaddr pa = 0;
- int prot;
+ int prot, prot2;
bool pmp_violation = false;
bool m_mode_two_stage = false;
bool hs_mode_two_stage = false;
@@ -755,13 +755,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
/* Second stage lookup */
im_address = pa;
- ret = get_physical_address(env, &pa, &prot, im_address,
+ ret = get_physical_address(env, &pa, &prot2, im_address,
access_type, mmu_idx, false, true);
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
- __func__, im_address, ret, pa, prot);
+ __func__, im_address, ret, pa, prot2);
+
+ prot &= prot2;
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
--
2.26.1.301.g55bc3eb7cb9-goog
- [PULL] RISC-V Patches for 5.0-rc4, Palmer Dabbelt, 2020/04/21
- [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs, Palmer Dabbelt, 2020/04/21
- [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags, Palmer Dabbelt, 2020/04/21
- [PULL 4/6] riscv/sifive_u: Fix up file ordering, Palmer Dabbelt, 2020/04/21
- [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine, Palmer Dabbelt, 2020/04/21
- [PULL 3/6] riscv: AND stage-1 and stage-2 protection flags,
Palmer Dabbelt <=
- [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC, Palmer Dabbelt, 2020/04/21
- Re: [PULL] RISC-V Patches for 5.0-rc4, Peter Maydell, 2020/04/21