Re: [PATCH for-5.0?] target/arm: Fix ID_MMFR4 value on AArch64 'max' CPU

[Philippe Mathieu-Daudé]

On Wed, Apr 22, 2020 at 7:41 PM Philippe Mathieu-Daudé
<address@hidden> wrote:
>
> On 4/22/20 2:45 PM, Peter Maydell wrote:
> > In commit 41a4bf1feab098da4cd the added code to set the CNP
> > field in ID_MMFR4 for the AArch64 'max' CPU had a typo
> > where it used the wrong variable name, resulting in ID_MMFR4
> > fields AC2, XNX and LSM being wrong. Fix the typo.
> >
> > Fixes: 41a4bf1feab098da4cd
> > Reported-by: Laurent Desnogues <address@hidden>
>
> Nice testing/catch Laurent!
>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
>
> > Signed-off-by: Peter Maydell <address@hidden>
> > ---
> > maybe 5.0 just because it's so trivial. I dunno...

BTW FWIW LGTM...

> >
> > There's also an error where we use the uint32_t u variable
> > to update the 64-bit ID_AA64DFR0 register, but that's harmless
> > because as it happens the top 32 bits of that register are
> > all zeroes anyway, so we can just fix that in 5.1.
> >
> >   target/arm/cpu64.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> > index 62d36f9e8d3..95d0c8c101a 100644
> > --- a/target/arm/cpu64.c
> > +++ b/target/arm/cpu64.c
> > @@ -705,7 +705,7 @@ static void aarch64_max_initfn(Object *obj)
> >           u = cpu->isar.id_mmfr4;
> >           u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
> >           u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
> > -        u = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
> > +        u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
> >           cpu->isar.id_mmfr4 = u;
> >
> >           u = cpu->isar.id_aa64dfr0;
> >