[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bi
From: |
Alistair Francis |
Subject: |
[PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option |
Date: |
Wed, 29 Apr 2020 11:28:55 -0700 |
From: Anup Patel <address@hidden>
This patch extends Spike machine support to allow loading OpenSBI
firmware (fw_jump.elf) separately using -bios option.
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/spike.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 98697a244e..e7908b88fe 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -45,6 +45,12 @@
#include <libfdt.h>
+#if defined(TARGET_RISCV32)
+# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
+#else
+# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
+#endif
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -187,8 +193,24 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
mask_rom);
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME,
+ memmap[SPIKE_DRAM].base,
+ htif_symbol_callback);
+
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
+ uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
+ htif_symbol_callback);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
}
/* reset vector */
--
2.26.2
- [PULL 01/14] riscv/sifive_u: Fix up file ordering, (continued)
- [PULL 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL 05/14] riscv: AND stage-1 and stage-2 protection flags, Alistair Francis, 2020/04/29
- [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option,
Alistair Francis <=
- [PULL 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL 00/14] RISC-V Patch Queue for 5.1, Peter Maydell, 2020/04/29