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[PULL 24/31] target/arm: Restrict the Address Translate write operation
From: |
Peter Maydell |
Subject: |
[PULL 24/31] target/arm: Restrict the Address Translate write operation to TCG accel |
Date: |
Thu, 30 Apr 2020 12:51:35 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
Under KVM these registers are written by the hardware.
Restrict the writefn handlers to TCG to avoid when building
without TCG:
LINK aarch64-softmmu/qemu-system-aarch64
target/arm/helper.o: In function `do_ats_write':
target/arm/helper.c:3524: undefined reference to `raise_exception'
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7e9ea5d20fa..dfefb9b3d9b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3442,6 +3442,7 @@ static CPAccessResult ats_access(CPUARMState *env, const
ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+#ifdef CONFIG_TCG
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
MMUAccessType access_type, ARMMMUIdx mmu_idx)
{
@@ -3602,9 +3603,11 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
}
return par64;
}
+#endif /* CONFIG_TCG */
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
+#ifdef CONFIG_TCG
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
ARMMMUIdx mmu_idx;
@@ -3664,17 +3667,26 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
par64 = do_ats_write(env, value, access_type, mmu_idx);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
+#else
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+#endif /* CONFIG_TCG */
}
static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+#ifdef CONFIG_TCG
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
+#else
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+#endif /* CONFIG_TCG */
}
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3689,6 +3701,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env,
const ARMCPRegInfo *ri,
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+#ifdef CONFIG_TCG
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
ARMMMUIdx mmu_idx;
int secure = arm_is_secure_below_el3(env);
@@ -3728,6 +3741,10 @@ static void ats_write64(CPUARMState *env, const
ARMCPRegInfo *ri,
}
env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
+#else
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+#endif /* CONFIG_TCG */
}
#endif
--
2.20.1
- [PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts, (continued)
- [PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts, Peter Maydell, 2020/04/30
- [PULL 16/31] hw/arm/xilinx_zynq: connect uart clocks to slcr, Peter Maydell, 2020/04/30
- [PULL 15/31] hw/char/cadence_uart: add clock support, Peter Maydell, 2020/04/30
- [PULL 18/31] hw/arm: versal: Setup the ADMA with 128bit bus-width, Peter Maydell, 2020/04/30
- [PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors, Peter Maydell, 2020/04/30
- [PULL 20/31] net: cadence_gem: clear RX control descriptor, Peter Maydell, 2020/04/30
- [PULL 17/31] qdev-monitor: print the device's clock with info qtree, Peter Maydell, 2020/04/30
- [PULL 22/31] hw/arm/virt: dt: move creation of /secure-chosen to create_fdt(), Peter Maydell, 2020/04/30
- [PULL 21/31] target/arm: Vectorize integer comparison vs zero, Peter Maydell, 2020/04/30
- [PULL 23/31] hw/arm/virt: dt: add kaslr-seed property, Peter Maydell, 2020/04/30
- [PULL 24/31] target/arm: Restrict the Address Translate write operation to TCG accel,
Peter Maydell <=
- [PULL 25/31] target/arm: Make cpu_register() available for other files, Peter Maydell, 2020/04/30
- [PULL 26/31] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[], Peter Maydell, 2020/04/30
- [PULL 27/31] target/arm/cpu: Update coding style to make checkpatch.pl happy, Peter Maydell, 2020/04/30
- [PULL 28/31] device_tree: Allow name wildcards in qemu_fdt_node_path(), Peter Maydell, 2020/04/30
- [PULL 29/31] device_tree: Constify compat in qemu_fdt_node_path(), Peter Maydell, 2020/04/30
- [PULL 31/31] hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes, Peter Maydell, 2020/04/30
- [PULL 30/31] hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102, Peter Maydell, 2020/04/30
- Re: [PULL 00/31] target-arm queue, no-reply, 2020/04/30