[PATCH V3 14/14] KVM: MIPS: Enable KVM support for Loongson-3

[Huacai Chen]

This patch enable KVM support for Loongson-3 by selecting HAVE_KVM, but
only enable KVM/VZ on Loongson-3A R4+ (because VZ of early processors
are incomplete). Besides, Loongson-3 support SMP guests, so we clear the
linked load bit of LLAddr in kvm_vz_vcpu_load() if the guest has more
than one VCPUs.

Signed-off-by: Huacai Chen <address@hidden>
Co-developed-by: Jiaxun Yang <address@hidden>
---
 arch/mips/Kconfig            | 1 +
 arch/mips/kernel/cpu-probe.c | 1 +
 arch/mips/kvm/vz.c           | 2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9f15539..9c4bdac 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1470,6 +1470,7 @@ config CPU_LOONGSON64
        select MIPS_L1_CACHE_SHIFT_6
        select GPIOLIB
        select SWIOTLB
+       select HAVE_KVM
        help
                The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of 
processor
                cores implements the MIPS64R2 instruction set with many 
extensions,
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index be1b556..4432442 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2008,6 +2008,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips 
*c, unsigned int cpu)
                c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
                        MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
+               c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is 
incomplete */
                break;
        case PRID_IMP_LOONGSON_64G:
                c->cputype = CPU_LOONGSON64;
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index fc0f8d5..5f877a9 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -2695,7 +2695,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int 
cpu)
         * prevents a SC on the next VCPU from succeeding by matching a LL on
         * the previous VCPU.
         */
-       if (cpu_guest_has_rw_llb)
+       if (vcpu->kvm->created_vcpus > 1)
                write_gc0_lladdr(0);
 
        return 0;
-- 
2.7.0