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[PATCH v3 08/11] net: cadnece_gem: Update irq_read_clear field of design
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From: |
Sai Pavan Boddu |
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Subject: |
[PATCH v3 08/11] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg |
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Date: |
Fri, 8 May 2020 16:30:42 +0530 |
Advertise support of clear-on-read for ISR registers.
Signed-off-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 45c50ab..65b29cc 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1344,7 +1344,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_TXPARTIALSF] = 0x000003ff;
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
s->regs[GEM_MODID] = s->revision;
- s->regs[GEM_DESCONF] = 0x02500111;
+ s->regs[GEM_DESCONF] = 0x02D00111;
s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
--
2.7.4
- [PATCH v3 06/11] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, (continued)
- [PATCH v3 06/11] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, Sai Pavan Boddu, 2020/05/08
- [PATCH v3 05/11] net: cadence_gem: Set ISR according to queue in use, Sai Pavan Boddu, 2020/05/08
- [PATCH v3 09/11] net: cadence_gem: Update the reset value for interrupt mask register, Sai Pavan Boddu, 2020/05/08
- [PATCH v3 07/11] net: cadence_gem: Add support for jumbo frames, Sai Pavan Boddu, 2020/05/08
- [PATCH v3 10/11] net: cadence_gem: TX_LAST bit should be set by guest, Sai Pavan Boddu, 2020/05/08
- [PATCH v3 11/11] net: cadence_gem: Fix RX address filtering, Sai Pavan Boddu, 2020/05/08
- [PATCH v3 08/11] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg,
Sai Pavan Boddu <=