Re: [PATCH for-5.1 V3 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

[Aleksandar Markovic]

нед, 3. мај 2020. у 12:24 Huacai Chen <address@hidden> је написао/ла:
>
> Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
> IP3 delivery as well, because Loongson-3 based machine use both IRQ2
> (CPU's IP2) and IRQ3 (CPU's IP3).
>
> Signed-off-by: Huacai Chen <address@hidden>
> Co-developed-by: Jiaxun Yang <address@hidden>
> ---

Reviewed-by: Aleksandar Markovic <address@hidden>

>  hw/mips/mips_int.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
> index 796730b..982ce34 100644
> --- a/hw/mips/mips_int.c
> +++ b/hw/mips/mips_int.c
> @@ -48,14 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int irq, 
> int level)
>      if (level) {
>          env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
>
> -        if (kvm_enabled() && irq == 2) {
> +        if (kvm_enabled() && (irq == 2 || irq == 3)) {
>              kvm_mips_set_interrupt(cpu, irq, level);
>          }
>
>      } else {
>          env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
>
> -        if (kvm_enabled() && irq == 2) {
> +        if (kvm_enabled() && (irq == 2 || irq == 3)) {
>              kvm_mips_set_interrupt(cpu, irq, level);
>          }
>      }
> --
> 2.7.0
>